diff --git a/apps/baremetal/mpam_main.c b/apps/baremetal/mpam_main.c index 1c653696..4afad6a9 100644 --- a/apps/baremetal/mpam_main.c +++ b/apps/baremetal/mpam_main.c @@ -23,49 +23,17 @@ #include "val/include/acs_memory.h" #include "acs.h" -/* - * Build-time selection arrays for the MPAM bare-metal (non rule-based) path. - */ -extern uint32_t g_skip_array[]; -extern const uint32_t g_skip_array_len; -extern uint32_t g_test_array[]; -extern const uint32_t g_test_array_len; -extern uint32_t g_module_array[]; -extern const uint32_t g_module_array_len; - -/* MPAM bare-metal globals local. */ -uint32_t *g_skip_test_num; -uint32_t g_num_skip; -uint32_t *g_execute_tests; -uint32_t g_num_tests; -uint32_t *g_execute_modules; -uint32_t g_num_modules; -uint32_t g_execute_secure = 0; - static void free_mpam_mem(void) { val_free_shared_mem(); val_mpam_free_info_table(); + val_srat_free_info_table(); + val_hmat_free_info_table(); val_pcc_free_info_table(); - - if (acs_is_module_enabled(ACS_MPAM_MEMORY_TEST_NUM_BASE)) { - val_srat_free_info_table(); - val_hmat_free_info_table(); - } - - if (acs_is_module_enabled(ACS_MPAM_CACHE_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MONITOR_TEST_NUM_BASE)) - val_cache_free_info_table(); - - if (acs_is_module_enabled(ACS_MPAM_ERROR_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_CACHE_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MONITOR_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MEMORY_TEST_NUM_BASE)) { - val_iovirt_free_info_table(); - val_gic_free_info_table(); - } - + val_cache_free_info_table(); + val_iovirt_free_info_table(); + val_gic_free_info_table(); val_pe_free_info_table(); } @@ -80,19 +48,22 @@ apply_mpam_defaults(acs_run_request_t *ctx, acs_execution_policy_t *policy) policy->print_level = PLATFORM_OVERRIDE_PRINT_LEVEL; policy->print_mmio = 0; - ctx->arch_selection = ARCH_NONE; - - /* Use build-time selection arrays (legacy non-rulebase mechanism). */ - g_skip_test_num = g_skip_array; - g_num_skip = g_skip_array_len; - g_execute_tests = g_test_array; - g_num_tests = g_test_array_len; - g_execute_modules = g_module_array; - g_num_modules = g_module_array_len; + + if (ctx->rule_count == 0) + ctx->arch_selection = ARCH_SYS_MPAM; + + ctx->level_value = MPAM_VERSION_B_c; + if (ctx->level_filter_mode == LVL_FILTER_NONE) + ctx->level_filter_mode = LVL_FILTER_MAX; + + if (ctx->level_value >= MPAM_VERSION_SENTINEL) { + val_print(ERROR, "\nInvalid MPAM version value (%d)", ctx->level_value); + return ACS_STATUS_FAIL; + } + g_acs_tests_total = 0; g_acs_tests_pass = 0; g_acs_tests_fail = 0; - g_execute_secure = 0; return ACS_STATUS_PASS; } @@ -143,15 +114,6 @@ ShellAppMainmpam(void) val_print(INFO, "\nSkipping MMU setup/enable (ACS_ENABLE_MMU=0)"); #endif - if (!acs_is_module_enabled(ACS_MPAM_REGISTER_TEST_NUM_BASE) && - !acs_is_module_enabled(ACS_MPAM_CACHE_TEST_NUM_BASE) && - !acs_is_module_enabled(ACS_MPAM_MONITOR_TEST_NUM_BASE) && - !acs_is_module_enabled(ACS_MPAM_ERROR_TEST_NUM_BASE) && - !acs_is_module_enabled(ACS_MPAM_MEMORY_TEST_NUM_BASE)) { - val_print(INFO, "\n No MPAM modules selected. Skipping table init/tests.\n"); - goto print_test_status; - } - val_print(INFO, "\nCreating Platform Information Tables"); status = createPeInfoTable(); @@ -168,22 +130,15 @@ ShellAppMainmpam(void) if (status) goto exit_acs; - if (acs_is_module_enabled(ACS_MPAM_ERROR_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_CACHE_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MONITOR_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MEMORY_TEST_NUM_BASE)) - createIoVirtInfoTable(); + createIoVirtInfoTable(); - if (acs_is_module_enabled(ACS_MPAM_CACHE_TEST_NUM_BASE) || - acs_is_module_enabled(ACS_MPAM_MONITOR_TEST_NUM_BASE)) - createCacheInfoTable(); + createCacheInfoTable(); createPccInfoTable(); - if (acs_is_module_enabled(ACS_MPAM_MEMORY_TEST_NUM_BASE)) { - createHmatInfoTable(); - createSratInfoTable(); - } + createHmatInfoTable(); + + createSratInfoTable(); createMpamInfoTable(); val_mpam_update_msc_device_names(); @@ -200,17 +155,23 @@ ShellAppMainmpam(void) context_saved = 1; val_pe_initialize_default_exception_handler(val_pe_default_esr); - status |= val_mpam_execute_register_tests(); - status |= val_mpam_execute_cache_tests(); - status |= val_mpam_execute_error_tests(); - status |= val_mpam_execute_membw_tests(); + if ((ctx->rule_count > 0 && ctx->rule_list != NULL) || + (ctx->arch_selection != ARCH_NONE)) { + filter_rule_list_by_cli(ctx); + if (ctx->rule_count == 0 || ctx->rule_list == NULL) { + val_print(ERROR, "\nRule list empty, nothing to execute.\n"); + status = ACS_STATUS_FAIL; + goto print_test_status; + } + + run_tests(ctx); + } else { + val_print(ERROR, "\nInvalid rule list or architecture selected.\n"); + status = ACS_STATUS_FAIL; + } print_test_status: - val_print(ERROR, "\n ------------------------------------------------------- \n"); - val_print(ERROR, " Total Tests run = %4d;", g_acs_tests_total); - val_print(ERROR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ERROR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ERROR, " --------------------------------------------------------- \n"); + val_print_acs_test_status_summary(); val_print(INFO, "\n *** MPAM tests complete. Reset the system. *** \n\n"); diff --git a/apps/uefi/Mpam.inf b/apps/uefi/Mpam.inf index eebb35c7..0fb23c58 100644 --- a/apps/uefi/Mpam.inf +++ b/apps/uefi/Mpam.inf @@ -35,6 +35,8 @@ ../ ../../ app.c + acs_globals.c + acs_helpers.c mpam_main.c ../../test_pool/mpam/reg001.c ../../test_pool/mpam/reg002.c diff --git a/apps/uefi/mpam_main.c b/apps/uefi/mpam_main.c index 786845b3..c5ab05b0 100644 --- a/apps/uefi/mpam_main.c +++ b/apps/uefi/mpam_main.c @@ -32,111 +32,36 @@ #include "acs.h" UINT32 g_execute_secure; -UINT32 *g_skip_test_num; -UINT32 g_num_skip; UINT32 g_acs_tests_total; UINT32 g_acs_tests_pass; UINT32 g_acs_tests_fail; -UINT64 g_stack_pointer; -UINT64 g_exception_ret_addr; -UINT64 g_ret_addr; -UINT32 g_curr_module; -UINT32 g_enable_module; UINT32 *g_execute_tests; UINT32 g_num_tests = 0; UINT32 *g_execute_modules; UINT32 g_num_modules = 0; -SHELL_FILE_HANDLE g_acs_log_file_handle; -SHELL_FILE_HANDLE g_dtb_log_file_handle; - -VOID -FlushImage ( - VOID - ) -{ - - EFI_LOADED_IMAGE_PROTOCOL *ImageInfo; - EFI_STATUS Status; - Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **)&ImageInfo); - if(EFI_ERROR (Status)) { - return; - } - - val_pe_cache_clean_range((UINT64)ImageInfo->ImageBase, (UINT64)ImageInfo->ImageSize); -} - -UINT32 -createPeInfoTable ( -) -{ - UINT32 Status; - UINT64 *PeInfoTable; - - PeInfoTable = val_aligned_alloc(SIZE_4K, PE_INFO_TBL_SZ); - - Status = val_pe_create_info_table(PeInfoTable); - - return Status; -} - -UINT32 -createGicInfoTable ( -) -{ - UINT32 Status; - UINT64 *GicInfoTable; - - GicInfoTable = val_aligned_alloc(SIZE_4K, GIC_INFO_TBL_SZ); - - Status = val_gic_create_info_table(GicInfoTable); - - return Status; -} - -VOID -createMpamInfoTable( -) -{ - UINT64 *MpamInfoTable; - - MpamInfoTable = val_aligned_alloc(SIZE_4K, MPAM_INFO_TBL_SZ); - - val_mpam_create_info_table(MpamInfoTable); -} - - -VOID -createHmatInfoTable( -) +static UINT32 +apply_cli_defaults(acs_run_request_t *ctx) { - UINT64 *HmatInfoTable; + if (ctx == NULL) + return ACS_STATUS_FAIL; - HmatInfoTable = val_aligned_alloc(SIZE_4K, HMAT_INFO_TBL_SZ); - - val_hmat_create_info_table(HmatInfoTable); -} - -VOID -createSratInfoTable( -) -{ - UINT64 *SratInfoTable; - - SratInfoTable = val_aligned_alloc(SIZE_4K, SRAT_INFO_TBL_SZ); - - val_srat_create_info_table(SratInfoTable); -} + if (ctx->rule_count == 0) { + ctx->arch_selection = ARCH_SYS_MPAM; + } -VOID -createPccInfoTable( -) -{ - UINT64 *PccInfoTable; + if (ctx->level_filter_mode == LVL_FILTER_NONE) { + ctx->level_filter_mode = LVL_FILTER_MAX; + ctx->level_value = MPAM_VERSION_B_c; + } - PccInfoTable = val_aligned_alloc(SIZE_4K, PCC_INFO_TBL_SZ); + if (ctx->level_value >= MPAM_VERSION_SENTINEL) { + val_print(ERROR, "\nInvalid MPAM version value passed (%d), ", ctx->level_value); + val_print(ERROR, "value should be less than %d.", MPAM_VERSION_SENTINEL); + return ACS_STATUS_FAIL; + } - val_pcc_create_info_table(PccInfoTable); + return ACS_STATUS_PASS; } VOID @@ -150,17 +75,6 @@ createIovirtInfoTable( val_iovirt_create_info_table(IoVirtInfoTable); } -VOID -createCacheInfoTable( -) -{ - UINT64 *CacheInfoTable; - - CacheInfoTable = val_aligned_alloc(SIZE_4K, CACHE_INFO_TBL_SZ); - - val_cache_create_info_table(CacheInfoTable); -} - VOID FreeMpamAcsMem ( ) @@ -182,27 +96,36 @@ HelpMsg ( ) { - Print (L"\nUsage: Mpam.efi [-v ] | [-f ] | [-s] | [-skip ]| [-t ] | [-m ]\n" + Print (L"\nUsage: Mpam.efi [options]\n" "Options:\n" - "-v Verbosity of the Prints\n" - " 1 shows all prints, 5 shows Errors\n" "-f Name of the log file to record the test results in\n" - "-skip Test(s) to be skipped\n" - " To skip a module, use Model_ID as mentioned in user guide\n" - " To skip a particular test within a module, use the exact testcase number\n" - "-t If Test ID(s) set, will only run the specified test(s), all others will be skipped.\n" - "-m If Module ID(s) set, will only run the specified module(s), all others will be skipped.\n" + "-h, -help\n" + " Print this message\n" + "-l Run SYS-MPAM rules for the specified MPAM architecture version\n" + " Supported MPAM_VERSION_e values:\n" + " 1 - MPAM_VERSION_B_c\n" + "-m Run only the specified modules (comma-separated names).\n" + " Accepted values: CACHE, REG, ERROR, MBWU\n" + "-r Run tests for passed comma-separated SYS-MPAM rule IDs or a rules file\n" + " Example: -r RBDJXQ\n" + "-skip SYS-MPAM rule ID(s) to be skipped (comma-separated, like -r)\n" + "-skipmodule\n" + " Skip the specified modules (comma-separated names).\n" + "-v Verbosity of the prints\n" + " 1 prints all, 5 prints only the errors\n" ); } CONST SHELL_PARAM_ITEM ParamList[] = { - {L"-v" , TypeValue}, // -v # Verbosity of the Prints. 1 shows all prints, 5 shows Errors - {L"-f" , TypeValue}, // -f # Name of the log file to record the test results in. - {L"-skip" , TypeValue}, // -skip # test(s) to skip execution - {L"-help" , TypeFlag}, // -help # help : info about commands - {L"-h" , TypeFlag}, // -h # help : info about commands - {L"-t" , TypeValue}, // -t # Test to be run - {L"-m" , TypeValue}, // -m # Module to be run + {L"-f", TypeValue}, + {L"-h", TypeFlag}, + {L"-help", TypeFlag}, + {L"-l", TypeValue}, + {L"-m", TypeValue}, + {L"-r", TypeValue}, + {L"-skip", TypeValue}, + {L"-skipmodule", TypeValue}, + {L"-v", TypeValue}, {NULL , TypeMax} }; @@ -214,182 +137,20 @@ CONST SHELL_PARAM_ITEM ParamList[] = { * @retval 0 The application exited normally. * @retval Other An error occurred. */ -UINT32 -command_init () -{ - - LIST_ENTRY *ParamPackage; - CONST CHAR16 *CmdLineArg; - CHAR16 *ProbParam; - UINT32 Status; - UINT32 i; - acs_execution_policy_t *policy; - - acs_reset_execution_policy(); - policy = acs_get_execution_policy_mut(); - - /* Process Command Line arguments */ - Status = ShellInitialize(); - Status = ShellCommandLineParse (ParamList, &ParamPackage, &ProbParam, TRUE); - if (Status) { - Print(L"Shell command line parse error %x\n", Status); - Print(L"Unrecognized option %s passed\n", ProbParam); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - - // Options with Values - if (ShellCommandLineGetFlag (ParamPackage, L"-skip")) { - CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-skip"); - if (CmdLineArg == NULL) - { - Print(L"Invalid parameter passed for -skip\n", 0); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - else - { - Status = gBS->AllocatePool(EfiBootServicesData, - StrLen(CmdLineArg), - (VOID **) &g_skip_test_num); - if (EFI_ERROR(Status)) - { - Print(L"Allocate memory for -skip failed\n", 0); - return ACS_PARSE_SKIP_RUN; - } - - g_skip_test_num[0] = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg+0)); - for (i = 0; i < StrLen(CmdLineArg); i++) { - if(*(CmdLineArg+i) == L',') { - g_skip_test_num[++g_num_skip] = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg+i+1)); - } - } - - g_num_skip++; - } - } - - /* Options with Values */ - CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-v"); - if (CmdLineArg == NULL) { - policy->print_level = G_PRINT_LEVEL; - } else { - policy->print_level = StrDecimalToUintn(CmdLineArg); - if (policy->print_level > 5) { - policy->print_level = G_PRINT_LEVEL; - } - } - - /* Options with Values */ - CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-f"); - if (CmdLineArg == NULL) { - g_acs_log_file_handle = NULL; - } else { - Status = ShellOpenFileByName(CmdLineArg, &g_acs_log_file_handle, - EFI_FILE_MODE_WRITE | EFI_FILE_MODE_READ | EFI_FILE_MODE_CREATE, 0x0); - if (EFI_ERROR(Status)) { - Print(L"Failed to open log file %s\n", CmdLineArg); - g_acs_log_file_handle = NULL; - } - } - - // Options with Values - if (ShellCommandLineGetFlag (ParamPackage, L"-t")) { - CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-t"); - if (CmdLineArg == NULL) - { - Print(L"Invalid parameter passed for -t\n", 0); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - else - { - Status = gBS->AllocatePool(EfiBootServicesData, - StrLen(CmdLineArg), - (VOID **) &g_execute_tests); - if (EFI_ERROR(Status)) - { - Print(L"Allocate memory for -t failed\n", 0); - return ACS_PARSE_SKIP_RUN; - } - - /* Check if the first value to -t is a decimal character. */ - if (!ShellIsDecimalDigitCharacter(*CmdLineArg)) { - Print(L"Invalid parameter passed for -t\n", 0); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - - g_execute_tests[0] = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg + 0)); - for (i = 0; i < StrLen(CmdLineArg); i++) { - if (*(CmdLineArg + i) == L',') { - g_execute_tests[++g_num_tests] = StrDecimalToUintn( - (CONST CHAR16 *)(CmdLineArg + i + 1)); - } - } - - g_num_tests++; - } - } - - if (ShellCommandLineGetFlag (ParamPackage, L"-m")) { - CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-m"); - if (CmdLineArg == NULL) - { - Print(L"Invalid parameter passed for -m\n", 0); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - else - { - Status = gBS->AllocatePool(EfiBootServicesData, - StrLen(CmdLineArg), - (VOID **) &g_execute_modules); - if (EFI_ERROR(Status)) - { - Print(L"Allocate memory for -m failed\n", 0); - return ACS_PARSE_SKIP_RUN; - } - - /* Check if the first value to -m is a decimal character. */ - if (!ShellIsDecimalDigitCharacter(*CmdLineArg)) { - Print(L"Invalid parameter passed for -m\n", 0); - HelpMsg(); - return SHELL_INVALID_PARAMETER; - } - - g_execute_modules[0] = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg + 0)); - for (i = 0; i < StrLen(CmdLineArg); i++) { - if (*(CmdLineArg + i) == L',') { - g_execute_modules[++g_num_modules] = StrDecimalToUintn( - (CONST CHAR16 *)(CmdLineArg + i + 1)); - } - } - - g_num_modules++; - } - } - - /* Options with Values */ - if ((ShellCommandLineGetFlag (ParamPackage, L"-help")) || (ShellCommandLineGetFlag (ParamPackage, L"-h"))) { - HelpMsg(); - return ACS_PARSE_SKIP_RUN; - } - - /* Initialize global counters */ - g_acs_tests_total = 0; - g_acs_tests_pass = 0; - g_acs_tests_fail = 0; - - return (0); -} - UINT32 execute_tests() { VOID *branch_label; UINT32 Status; UINT32 msc_node_cnt; + acs_run_request_t *ctx; + + ctx = acs_get_run_request_mut(); + Status = apply_cli_defaults(ctx); + if (Status != ACS_STATUS_PASS) { + acs_release_run_request(ctx); + return Status; + } branch_label = &&print_test_status; val_pe_context_save(AA64ReadSp(), (uint64_t)branch_label); @@ -403,7 +164,7 @@ execute_tests() Print(L"\nCreating Platform Information Tables"); Status = createPeInfoTable(); if (Status) - return Status; + goto cleanup; /* check if PE supports MPAM extension, else skip all MPAM tests */ if (val_pe_feat_check(PE_FEAT_MPAM)) { @@ -414,7 +175,7 @@ execute_tests() Status = createGicInfoTable(); if (Status) - return Status; + goto cleanup; createIovirtInfoTable(); @@ -446,22 +207,19 @@ execute_tests() val_pe_initialize_default_exception_handler(val_pe_default_esr); FlushImage(); - Status |= val_mpam_execute_register_tests(); - - Status |= val_mpam_execute_cache_tests(); + if ((ctx->rule_count > 0 && ctx->rule_list != NULL) || (ctx->arch_selection != ARCH_NONE)) { + filter_rule_list_by_cli(ctx); + if (ctx->rule_count == 0 || ctx->rule_list == NULL) + goto print_test_status; - Status |= val_mpam_execute_error_tests(); - - Status |= val_mpam_execute_membw_tests(); - - FreeMpamAcsMem(); + print_selection_summary(); + run_tests(ctx); + } else { + val_print(INFO, "\nNo rules selected for execution.\n"); + } print_test_status: - val_print(ERROR, "\n ------------------------------------------------------- \n"); - val_print(ERROR, " Total Tests run = %4d;", g_acs_tests_total); - val_print(ERROR, " Tests Passed = %4d", g_acs_tests_pass); - val_print(ERROR, " Tests Failed = %4d\n", g_acs_tests_fail); - val_print(ERROR, " --------------------------------------------------------- \n"); + val_print_acs_test_status_summary(); if (g_acs_log_file_handle) { ShellCloseFile(&g_acs_log_file_handle); @@ -469,7 +227,12 @@ execute_tests() Print(L"\n *** MPAM tests complete. Reset the system. *** \n\n"); +cleanup: + FreeMpamAcsMem(); + + acs_release_run_request(ctx); + val_pe_context_restore(AA64WriteSp(g_stack_pointer)); - return(0); + return Status; } diff --git a/docs/mpam/arm_sys-mpam_testcase_checklist.csv b/docs/mpam/arm_sys-mpam_testcase_checklist.csv new file mode 100644 index 00000000..4a43089f --- /dev/null +++ b/docs/mpam/arm_sys-mpam_testcase_checklist.csv @@ -0,0 +1,214 @@ +Specification Rule ID,BM,UEFI,Status,Tests,Notes +BDJXQ,Yes,Yes,COVERED,monitor001.c,Indirect: monitor001 programs request PARTID and PMG and verifies monitor accounting distinguishes the labels. +DDGSM,Yes,Yes,COVERED,-,No ACS check required: MSC may implement zero or more resource controls. ACS checks controls only when discovered. +RBCMK,Yes,Yes,COVERED,-,No ACS check required: MSC may implement zero or more monitors. ACS checks monitors only when discovered. +CFXGZ,Yes,Yes,COVERED,reg001.c,Direct: reg001 checks MPAM version EXT bit behavior. +FXVBB,Yes,Yes,COVERED,reg004.c,Direct: reg004 checks MPAM-for-RME feature requirements. +LRZGD,Yes,Yes,COVERED,-,No ACS check required: different MPAM architecture versions may coexist. ACS validates each discovered MSC against its advertised version. +PBSTK,Yes,Yes,COVERED,-,No ACS check required: base memory behavior rules always apply. No separate SYS-MPAM ACS check is required. +KXMHB,Yes,Yes,COVERED,reg004.c,"Indirect: non-secure PARTID space is exercised by ACS. Secure, Realm, and Root spaces cannot be directly validated from Non-secure execution." +CZHSY,,,NOT_COVERED,-,"Not testable: ACS cannot compare the same PARTID across Secure, Non-secure, Root, and Realm PARTID spaces." +RBWRS,,,NOT_COVERED,-,Not testable: ACS cannot access all PARTID spaces to prove each PARTID scope is space-local. +QKQCF,Yes,Yes,COVERED,-,"No ACS check required: Default PARTID 0 is architecturally defined; labeling non-MPAM requesters with it is permitted, not mandatory." +CZSZX,,,NOT_COVERED,-,Not testable: ACS cannot observe non-MPAM requester labeling to prove Default PMG 0 is used. +NVNHD,,,NOT_COVERED,-,"Not testable: requester-generation mechanism is system-wide. ACS cannot prove every PE, SMMU, GIC, and non-PE requester path." +SLJDR,,,NOT_COVERED,-,"Not testable: non-PE requester-generated PARTID space, PARTID, and PMG values are not directly observable by ACS." +VNVMD,,,NOT_COVERED,-,Not testable: non-MPAM requester default/system-specific labeling is not directly controllable or observable by ACS. +SJFGX,Yes,Yes,COVERED,-,No ACS check required: terminating completer has no downstream MPAM propagation to observe. No ACS runtime check is needed. +YPHLH,,,NOT_COVERED,-,Not testable: intermediate forwarding of MPAM information is fabric behavior. ACS cannot observe the downstream bundle directly. +RZCWR,,,NOT_COVERED,-,Not testable: buffered-request MPAM retention is internal. ACS cannot force or inspect a buffered request path. +MRWWK,Yes,Yes,COVERED,-,No ACS check required: conditional cache-internal storage rule. ACS checks observable controls and monitors when present. +XPPBS,Yes,Yes,COVERED,partition001.c,Indirect: cache partition tests exercise MSC response to request MPAM information. +CWTSC,Yes,Yes,COVERED,partition001.c,Indirect: partition tests exercise per-PARTID control lookup from request MPAM information. +JWKJD,,,NOT_COVERED,-,Not testable: cache-line MPAM metadata is internal. ACS cannot inspect the PARTID associated with each line. +SGBFN,,,NOT_COVERED,-,Not testable: cache eviction metadata is internal. ACS cannot prove PARTID preservation from inner to outer cache. +ZTFBQ,Yes,Yes,COVERED,reg001.c,"Indirect: reg001.c is used as a representative simple MMR access test. It uses the common MSC discovery/configuration path, including integrated PE MSCs if discovered." +JGWSM,Yes,Yes,COVERED,reg001.c,"Indirect: reg001.c is used as a representative Non-secure MMR access test. Secure, Realm, and Root PA spaces are not directly accessible to ACS." +LRNPR,Yes,Yes,COVERED,reg005.c,Indirect: reg004/reg005 check visible MPAM-for-RME and four-space capability. +VBHPB,Yes,Yes,COVERED,reg004.c,Indirect: reg004/reg005 cover visible PE/MSC capability; Non-secure traffic exercises Non-secure MPAM_SP propagation. +WZXPM,Yes,Yes,COVERED,reg001.c,Indirect: reg001.c is used as a representative Non-secure MPAM access test. ACS cannot directly observe MPAM_NS signal propagation or Secure-side traffic. +CBBRW,,,NOT_COVERED,-,Not testable: ACS cannot generate Secure traffic or check reserved Secure PARTID-space encodings. +CNQCS,,,NOT_COVERED,-,Not testable: ACS cannot observe 4-to-2 bridge reduction from Root/Realm MPAM_SP to MPAM_NS. +BHHCR,,,NOT_COVERED,-,Not testable: ACS cannot observe whether a 4-to-2 bridge uses static or dynamic reduction. +BSLZQ,,,NOT_COVERED,-,Not testable: ACS cannot observe 2-to-4 bridge expansion from MPAM_NS to MPAM_SP. +WBZST,,,NOT_COVERED,-,Not testable: ACS cannot prove bridge preservation of physical address space and PARTID space. +YWPPT,Yes,Yes,COVERED,-,No ACS check required: design statement for true two-space components. No separate ACS runtime check is needed. +BNKHP,,,NOT_COVERED,-,Not testable: mAP4SPTO2SP is Root PA-space only; Non-secure ACS cannot verify Root-only access. +KFDFD,,,NOT_COVERED,-,Not testable: external mapping register is Root PA-space only; Non-secure ACS cannot verify Root-only access. +XRQHH,,,NOT_COVERED,-,Not testable: ACS cannot observe fixed MPAM_SP to MPAM_NS bridge signal mapping. +VKQKB,,,NOT_COVERED,-,Not testable: ACS cannot identify or control all non-MPAM components to prove they do not propagate MPAM information. +TTSLQ,,,NOT_COVERED,-,Not testable: ACS does not control SMMU-attached requester traffic or observe its PARTID-space use. +RGSJV,,,NOT_COVERED,-,Not testable: completer interface behavior. ACS cannot observe whether MPAM information was dropped before a non-MPAM completer. +MFRGP,,,NOT_COVERED,-,Not testable: interconnect transport behavior. ACS cannot directly observe MPAM information on fabric links. +CYKPC,,,NOT_COVERED,-,Not testable: cache-line MPAM metadata is internal. ACS cannot inspect whether allocated lines store the request MPAM information. +KPNNZ,,,NOT_COVERED,-,Not testable: cache eviction propagation behavior. ACS cannot observe MPAM metadata passed with evicted cache lines. +JXRZM,Yes,Yes,COVERED,monitor001.c,Direct: CSUMON tests check cache-storage usage monitoring when implemented. +RHYKB,Yes,Yes,COVERED,monitor001.c,Direct: CSUMON PMG/PARTID filter tests check cache-storage accounting for matching criteria. +LQQJN,,,NOT_COVERED,-,Not testable: write-hit cache-line association is implementation-specific and cache-internal; ACS cannot observe the chosen association. +KBJPW,Yes,Yes,COVERED,-,"No ACS check required: write-hit portion update is permitted but not required, so there is no mandatory ACS behavior to check." +YBYPZ,Yes,Yes,COVERED,-,No ACS check required: reset/default-state behavior. SYS-MPAM ACS does not need a runtime check unless MPAM controls are discovered after boot. +CNGYT,Yes,Yes,COVERED,partition001.c,Direct: cache partitioning tests use CSU measurement to validate capacity-based partitioning behavior. +HHQWY,Yes,Yes,COVERED,error008.c,Direct: RIS tests exercise resource/control discovery and RIS-based control or monitor selection. +WSXSL,Yes,Yes,COVERED,"partition001.c, error008.c",Direct: partitioning and RIS tests exercise common resource-control selection using PARTID and RIS. +YQBMW,Yes,Yes,COVERED,error008.c,Direct: RIS tests exercise resource-instance selection and RIS-based control/monitor behavior. +YXZFG,Yes,Yes,COVERED,error008.c,"Indirect: RIS tests rely on discovered RIS values, but uniqueness is not the primary assertion." +DQNFB,Yes,Yes,COVERED,error008.c,"Indirect: RIS tests use RIS values in the 0..RIS_MAX range, but sparse assignment is not the primary assertion." +YGZYL,,,NOT_COVERED,-,"Gap: common controls can only be inferred when advertised at RIS 0. If identical controls appear for all RIS values, ACS cannot prove whether they are common or per-resource." +PLZWM,Yes,Yes,COVERED,error009.c,"Indirect: error009 exercises RIS no-control behavior, which covers unsupported non-zero RIS paths for partition controls." +DNNTB,Yes,Yes,COVERED,error010.c,Direct: monitor RIS tests use MSMON_CFG_MON_SEL.RIS to select resource-instance monitors. +LXXDB,Yes,Yes,COVERED,error010.c,Indirect: monitor RIS tests exercise RIS selection and unsupported monitor RIS paths; unassociated-monitor RIS 0 is not separately asserted. +MRZLG,Yes,Yes,COVERED,"error008.c, error010.c","Indirect: RIS tests use RIS_MAX and undefined RIS paths, but do not directly assert every permitted RIS decode rule." +NPVVN,Yes,Yes,COVERED,"error008.c, error009.c, error010.c, error011.c","Direct: RIS error tests validate undefined RIS, no-control, and no-monitor selected-resource cases." +HSFKH,Yes,Yes,COVERED,error012.c,Direct: error012 checks ID register HAS fields read zero and no ESR error for undefined RIS. +XRHKL,,,NOT_COVERED,-,Not testable: virtual PARTID resolution happens before the MSC. ACS cannot observe the pre-resolution virtual PARTID path. +GDMQZ,Yes,Yes,COVERED,reg005.c,Direct: reg005 checks MSC four-space capability when MPAM for RME is supported. +MMXWZ,Yes,Yes,COVERED,reg001.c,"Indirect: reg001.c is used as a representative MMR access test using MPAMF_BASE_ns from ACPI/platform data. Secure, Realm, and Root base fields are not validated." +QFCTM,Yes,Yes,COVERED,-,No ACS check required: allows controls and monitors to differ by PA space. No standalone ACS check is required. +CZMFT,Yes,Yes,COVERED,-,No ACS check required: defines when a resource can be partitioned. Actual controls are checked only when implemented. +XDZGT,Yes,Yes,COVERED,-,No ACS check required: describes possible RIS support for multiple resources. No standalone ACS check is required. +HLHYS,Yes,Yes,COVERED,-,No ACS check required: lists optional standard partitioning interfaces. ACS checks only implemented interfaces. +GVCBB,Yes,Yes,COVERED,partition001.c,Indirect: partitioning tests check IDR support bits before exercising each advertised control. +KWGHQ,Yes,Yes,COVERED,"partition001.c, mem001.c","Indirect: CPOR and MBWPBM tests use portion/PBM width and allocation behavior, but do not directly assert every generic portion property." +TZWJG,Yes,Yes,COVERED,feat001.c,Indirect: feat001 exercises PARTID enable/disable behavior; the global-to-MSC scope is not directly asserted. +VFJMZ,Yes,Yes,COVERED,feat001.c,Direct: feat001 verifies that a disabled PARTID allocates no resource or receives the lowest priority. +WFQFS,,,NOT_COVERED,-,Not testable: ACS cannot directly observe preserved hardware settings across PARTID disable/re-enable; behavior can only give indirect confidence. +GMCWW,,,NOT_COVERED,-,"Gap: needs a direct test to disable and re-enable one PARTID, then verify the effect across all RIS values." +CSLHH,,,NOT_COVERED,-,Gap: needs a direct PARTID narrowing test that disables a request PARTID and verifies the enabled status controls request behavior. +QFRFQ,Yes,Yes,COVERED,-,No ACS check required: defines normal enabled-control behavior. Feature-specific tests cover the implemented controls. +RNSLZ,Yes,Yes,COVERED,reg006.c,Direct: reg006 checks NFU is not implemented when PARTID narrowing is supported. +NJXHP,,,NOT_COVERED,-,Not testable: boot/reset enable state across all PARTIDs and spaces is not directly testable after firmware handoff. +XPPGG,Yes,Yes,COVERED,partition001.c,Direct: partition001 checks cache portion partitioning. +ZVTKX,Yes,Yes,COVERED,partition001.c,Indirect: partition001 exercises PARTID-based cache portion allocation. +RLHRV,Yes,Yes,COVERED,partition001.c,Indirect: partition001 programs CPOR through the generic portion-control model. +ZRSRZ,Yes,Yes,COVERED,partition001.c,Indirect: partition001 exercises CPBM permission bits through CPOR allocation behavior. +WMPLL,Yes,Yes,COVERED,partition001.c,Indirect: partition001 uses CPBM as the cache instance of the generic PBM model. +LPLMM,,,NOT_COVERED,-,"Not testable: cache-line portion after CPBM change is internal, and both reallocation and retained misallocation are allowed." +BDRCM,Yes,Yes,COVERED,partition004.c,Direct: partition004 checks cache associativity partitioning. +ZHBXH,Yes,Yes,COVERED,partition002.c,Direct: partition002 checks cache maximum-capacity partitioning. +SWNLN,Yes,Yes,COVERED,partition005.c,"Indirect: partition005 compares CMAX with SOFTLIM disabled/enabled, but does not directly prove unused capacity cannot be used above CMAX." +VZBFH,Yes,Yes,COVERED,partition005.c,Direct: partition005 checks CMAX soft-limit behavior. +CXZDR,Yes,Yes,COVERED,partition006.c,Direct: partition006 checks CMIN allocation-priority behavior. +FRTVY,Yes,Yes,COVERED,partition006.c,"Indirect: feat001, partition005, and partition006 exercise priority inputs, but not as a standalone priority table check." +DPZKC,Yes,Yes,COVERED,partition006.c,"Indirect: cache partition tests exercise allocation behavior, but do not directly assert each candidate-selection step." +DKYDB,Yes,Yes,COVERED,mem001.c,Direct: mem001 configures MBWPBM portions and validates bandwidth partition behavior with MBWU counters. +GYMDB,Yes,Yes,COVERED,mem001.c,Direct: mem001 programs BWPBM bits through MBWPBM configuration and validates permitted bandwidth behavior. +CFHQL,Yes,Yes,COVERED,mem001.c,Indirect: mem001 validates BWPBM behavior as a PBM-style bandwidth portion control. +HVRZS,Yes,Yes,COVERED,-,No ACS check required: lists optional bandwidth partitioning methods. ACS checks only methods that are implemented. +WKZBJ,Yes,Yes,COVERED,"mem002.c, mem003.c","Indirect: mem002 and mem003 validate MBWMIN/MBWMAX fraction behavior, but not every bandwidth control type in the table." +BPRDL,,,NOT_COVERED,-,Not testable: end-to-end bandwidth guarantee across concatenated MSCs is system-performance behavior that ACS cannot prove reliably. +WRXBV,Yes,Yes,COVERED,mem002.c,Direct: mem002 programs MBWMIN under contention and validates bandwidth behavior with MBWU counters. +NWVFK,Yes,Yes,COVERED,mem003.c,Direct: mem003 programs MBWMAX hard limits and validates bandwidth behavior with MBWU counters. +PKRGZ,,,NOT_COVERED,-,Gap: needs a combined MBWMIN+MBWMAX test; current tests validate each control separately. +VWHYW,Yes,Yes,COVERED,mem003.c,Indirect: mem002 and mem003 validate MBWMIN/MBWMAX behavior that relies on accounting-window tracking. +PWSWQ,,,NOT_COVERED,-,Not testable: accounting-window carry-over is internal and implementation-dependent; ACS cannot reliably prove unused bandwidth does not accumulate. +XSYFH,,,NOT_COVERED,-,Not testable: fixed accounting-window state is internal; ACS cannot reliably prove history clear and new-window behavior. +ZQXQL,,,NOT_COVERED,-,"Gap: priority partitioning for same-preference conflicts is testable, but no current mapped test covers it." +CMZNL,,,NOT_COVERED,-,Not testable: moving accounting-window history aging is internal; ACS cannot reliably prove request aging and removal behavior. +PXSBS,Yes,Yes,COVERED,-,No ACS check required: allows implementation-defined bandwidth tracking methods. No standalone ACS check is required. +ZDTLN,Yes,Yes,COVERED,-,No ACS check required: defines proportional stride as a generic proportional-control instance. No standalone ACS check is required. +ZFCRG,,,NOT_COVERED,-,"Gap: hAS_PROP advertisement is testable through MPAMF_MBW_IDR, but no current mapped test covers it." +TKBDC,,,NOT_COVERED,-,Gap: needs a combined proportional-stride + MBWMAX test; current tests cover MBWMAX only. +MSPZM,,,NOT_COVERED,-,"Gap: different priorities per MSC are testable through priority controls, but no current mapped test covers them." +JJKQP,,,NOT_COVERED,-,Not testable: upstream QoS priority arrival is fabric behavior. ACS cannot observe incoming interconnect priority signals. +NGDBL,,,NOT_COVERED,-,Not testable: priority override affects internal MSC operation and downstream transport priority; ACS cannot directly observe it. +MQRPH,Yes,Yes,COVERED,-,No ACS check required: internal priority partitioning is optional even when downstream priority exists. No mandatory ACS check. +RZDSR,Yes,Yes,COVERED,-,No ACS check required: downstream priority partitioning is optional even when internal priority exists. No mandatory ACS check. +MBNHC,,,NOT_COVERED,-,Not testable: response priority is downstream-to-upstream fabric behavior. ACS cannot directly observe response priority preservation. +JPLMZ,Yes,Yes,COVERED,-,No ACS check required: implementation-defined controls cannot be interpreted generically by ACS. No standalone ACS check is required. +DQTTD,Yes,Yes,COVERED,-,No ACS check required: PARTID narrowing support is optional. ACS checks narrowing behavior only if implemented. +RNWBS,,,NOT_COVERED,-,Gap: PARTID narrowing coverage still needs dedicated work; no current test proves this behavior. +GFYDF,,,NOT_COVERED,-,"Gap: iNTPARTID mapping programming is testable when narrowing exists, but no current mapped test covers it." +WCQKV,Yes,Yes,COVERED,-,No ACS check required: defines monitor types. ACS checks monitors only when the corresponding monitor type is implemented. +ZGGMX,Yes,Yes,COVERED,monitor001.c,Indirect: PARTID-based monitor tests use request PARTID filters; narrowing-specific behavior is not directly proven. +TMCXJ,,,NOT_COVERED,-,"Gap: top-level monitor RIS 0 access is testable, but no current mapped monitor test covers it." +YFMQP,Yes,Yes,COVERED,mem001.c,Direct: MBWU tests count payload bytes during memory workloads using MBWU monitor filters. +DLSGF,,,NOT_COVERED,-,"Gap: mBWU capture-event behavior is testable if capture registers exist, but no current mapped test covers it." +WHJQG,Yes,Yes,COVERED,monitor007.c,Direct: MBWU overflow tests prefill the counter near maximum and verify overflow behavior. +VLSJS,,,NOT_COVERED,-,Gap: no current ACS test explicitly verifies that MBWU_L VALUE is unscaled. +RYRQJ,Yes,Yes,COVERED,intr004.c,Direct: intr004 prefills MBWU_L near maximum and verifies long-counter overflow status/interrupt behavior. +QGXSZ,,,NOT_COVERED,-,Gap: no current ACS test triggers a CSU capture event; reg003 only rejects prohibited overflow-capture capability. +VJDKF,Yes,Yes,COVERED,"monitor001.c, mem001.c",Indirect: CSU and MBWU monitor tests read monitor VALUE only when NRDY is clear; no standalone structural check covers every monitor instance. +DSCQB,Yes,Yes,COVERED,"monitor005.c, monitor008.c",Indirect: MBWU tests verify VALUE advances/resumes and CSU tests read/write VALUE; no single test covers all VALUE-field behaviors. +FWCFZ,Yes,Yes,COVERED,monitor008.c,Direct: monitor008 writes MBWU VALUE to zero and verifies the counter resumes advancing after new traffic. +PVNHR,Yes,Yes,COVERED,monitor007.c,Direct: overflow tests write MBWU VALUE near maximum and verify hardware traffic advances the counter. +KCWDZ,Yes,Yes,COVERED,-,No ACS check required: monitor registers are permitted to be RO. No check is needed unless RW behavior is advertised. +XLWYW,Yes,Yes,COVERED,-,No ACS check required: rW monitor reprogramming without disable is permitted. No mandatory ACS behavior to check. +GKWNB,Yes,Yes,COVERED,monitor001.c,Indirect: CSU monitor tests reprogram PMG/PARTID criteria on the same monitor and continue reading VALUE after new traffic. +LRTGP,,,NOT_COVERED,-,Not testable: nRDY=1 after settings update can be too transient to observe reliably in ACS execution. +NXKSF,Yes,Yes,COVERED,monitor007.c,Direct: MBWU monitor tests fail if the monitor remains not-ready after update/wait paths. +FVFYC,Yes,Yes,COVERED,-,No ACS check required: automatic NRDY clear is not required for event monitors. No mandatory ACS check. +ZTXDS,Yes,Yes,COVERED,-,No ACS check required: software-defined NRDY use is permitted when automatic update is absent. No mandatory ACS check. +VBZTW,Yes,Yes,COVERED,monitor007.c,Direct: MBWU monitor tests wait MAX_NRDY_USEC and fail if NRDY remains set when the value is read. +FZHDC,,,NOT_COVERED,-,Gap: needs a capture-event test that reads the capture register NRDY copy and verifies monitor NRDY resets to 0 after capture. +YFVPY,,,NOT_COVERED,-,Gap: needs capture-event tests across monitor instances and capture registers; current tests only check prohibited capture capability. +NKTBN,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies immediate capture completion. +NWKJR,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies external capture distribution. +SQSMV,Yes,Yes,COVERED,-,No ACS check required: capture reset after copy is permitted but not required. No mandatory ACS check. +WQJKV,Yes,Yes,COVERED,monitor007.c,Direct: MBWU overflow tests drive VALUE past max and verify OFLOW_STATUS or OFLOW_STATUS_L is set. +XZXVK,Yes,Yes,COVERED,monitor007.c,"Indirect: monitor007 verifies post-overflow counter freeze/advance behavior, but does not directly assert the wrapped VALUE." +NDMMK,Yes,Yes,COVERED,monitor008.c,Direct: monitor008 clears OFLOW_STATUS through MSMON_CFG_MBWU_CTL and fails if the status remains set. +VBBTL,Yes,Yes,COVERED,"monitor005.c, monitor006.c","Direct: monitor tests disable the monitor, update MSMON_CFG control/value state, and verify the written state is usable." +XSTRM,Yes,Yes,COVERED,monitor007.c,Direct: monitor007 checks configurable monitor overflow behavior. +JCNST,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies linked capture-on-overflow behavior. +DFWFP,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies capture events stay local to one MSC. +GNQFY,Yes,Yes,COVERED,monitor008.c,Direct: monitor008 checks overflow status reset when monitor VALUE is written. +MGGJW,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies external capture distribution to all PARTID spaces. +HXNGD,,,NOT_COVERED,-,Gap: capture feature coverage is pending; no current ACS test verifies local capture distribution across address spaces. +RPGBQ,Yes,Yes,COVERED,-,No ACS check required: overflow linkage event is permitted for monitor types without capture-on-overflow. No mandatory ACS check. +MTGGZ,,,NOT_COVERED,-,Gap: capture feature coverage is pending; current OFLOW_FRZ test does not verify freeze caused by a capture event. +DYNFP,Yes,Yes,COVERED,error014.c,"Indirect: error014 triggers a second MPAM error after the first and verifies ESR updates, showing continued MSC error handling." +WHSLQ,Yes,Yes,COVERED,"error001.c, error003.c, error005.c, error008.c, error010.c, error014.c","Indirect: error tests validate multiple MPAMF_ESR ERRCODE table entries and selected captured fields, but not every table row or security-state case." +GVBGS,Yes,Yes,COVERED,error014.c,Direct: error014 generates a second MPAM error before clearing ESR and verifies ERRCODE updates. +QBKDG,Yes,Yes,COVERED,error013.c,Direct: error013 checks MPAMF_ESR.RIS reports the selector RIS that caused the error. +DLSCZ,Yes,Yes,COVERED,error001.c,Direct: error001 checks out-of-range PARTID_SEL error behavior. +ZWRQW,Yes,Yes,COVERED,error003.c,Direct: error003 checks MPAMCFG access behavior with out-of-range PARTID_SEL. +VKKDP,Yes,Yes,COVERED,error008.c,Direct: error008 checks undefined RIS handling in MPAMCFG_PART_SEL. +XTQZR,Yes,Yes,COVERED,"error012.c, error013.c","Direct: error012 reads MPAMF_IDR with undefined RIS, and error013 reads MPAMCFG after programming undefined RIS." +XDCDL,Yes,Yes,COVERED,error008.c,Direct: error008 checks undefined MPAMCFG_PART_SEL.RIS access and accepts ERRCODE 8 or RAZ/WI behavior. +JMLNM,,,NOT_COVERED,-,"Not testable: read value is architecturally UNKNOWN for these error cases, so ACS cannot validate a required value." +XMLDN,,,NOT_COVERED,-,"Not testable: resulting control setting is architecturally UNKNOWN for these write-error cases, so ACS cannot validate a required value." +VMTBP,Yes,Yes,COVERED,error005.c,Direct: error005 checks out-of-range monitor selector error behavior. +WXKWK,,,NOT_COVERED,-,"Not testable: read value is architecturally UNKNOWN for out-of-range MON_SEL, so ACS cannot validate a required value." +MGXDK,,,NOT_COVERED,-,"Not testable: post-write behavior is implementation-defined with UNKNOWN selector or WI, so ACS cannot validate one required result." +HJRZC,Yes,Yes,COVERED,error010.c,Direct: error010 checks undefined RIS handling in MSMON_CFG_MON_SEL. +SQTSJ,Yes,Yes,COVERED,error010.c,Direct: error010 validates ERRCODE 10 for undefined MSMON_CFG_MON_SEL.RIS; read value is UNKNOWN and not directly assertable. +VZWYW,,,NOT_COVERED,-,"Gap: needs a test that programs undefined MSMON_CFG_MON_SEL.RIS, then writes another MSMON register and checks ERRCODE 10 or allowed write behavior." +PNPQQ,Yes,Yes,COVERED,"error001.c, error003.c, error005.c",Indirect: implemented error tests exercise required reporting for selected supported error conditions. +SJFMB,Yes,Yes,COVERED,-,No ACS check required: hAS_ESR may be zero when no reportable errors exist. No standalone ACS check is required. +VYLZC,Yes,Yes,COVERED,-,No ACS check required: defines selector types used by later error rules. No standalone ACS check is required. +QBQJG,Yes,Yes,COVERED,-,No ACS check required: selector truncation behavior is permitted. ACS only checks invalid selector reporting when required. +PFNBV,Yes,Yes,COVERED,error001.c,Indirect: out-of-range selector tests indirectly exercise invalid selector detection. +CZZZK,Yes,Yes,COVERED,error007.c,Direct: error007 checks Unexpected INTERNAL error reporting when PARTID narrowing is supported. +HVNKJ,Yes,Yes,COVERED,-,No ACS check required: lists possible MPAM interrupt sources. ACS checks only implemented interrupt behavior. +TMMMD,Yes,Yes,COVERED,-,No ACS check required: four-space MSC choice of Secure or Non-secure error interrupt is permitted. No mandatory ACS check. +QDSPY,Yes,Yes,COVERED,-,No ACS check required: applies when no reportable error can occur or detection is optional. No standalone ACS check is required. +PPJSM,Yes,Yes,COVERED,-,No ACS check required: error interrupt type may be level-sensitive or edge-triggered. ACS checks the implemented type. +GLPPK,Yes,Yes,COVERED,intr001.c,Direct: intr001 checks level-sensitive error interrupt behavior. +NRGQD,,,NOT_COVERED,-,"Gap: level-sensitive error interrupt must not use MSI. This is testable if interrupt type is discoverable, but no current mapped test covers it." +KVGWS,Yes,Yes,COVERED,intr002.c,Direct: intr002 checks edge-triggered error interrupt behavior. +KVHTZ,,,NOT_COVERED,-,"Gap: mSI error interrupt requiring edge-triggered behavior is testable, but no current mapped test covers it." +ZRDMM,Yes,Yes,COVERED,-,No ACS check required: overflow interrupt support is optional. ACS checks overflow interrupts only if implemented. +YLCVK,Yes,Yes,COVERED,intr003.c,Direct: intr003 checks overflow interrupt generation conditions. +YJCDR,Yes,Yes,COVERED,intr005.c,Direct: intr005 checks MSI overflow interrupt edge-triggered requirement. +YVSNK,,,NOT_COVERED,-,"Gap: mSMON_OFLOW_SR summary behavior is testable if implemented, but no current mapped test covers it." +JLYJJ,Yes,Yes,COVERED,reg001.c,Indirect: reg001.c is used as a representative simple MMR access test. It discovers MSCs and reads memory-mapped MPAM registers. +MBDJF,,,NOT_COVERED,-,Not testable: 32-bit MMR single-copy atomicity is a bus atomicity property that ACS cannot prove reliably. +LVCGQ,Yes,Yes,COVERED,-,No ACS check required: greater-than-32-bit MMR atomicity is not required. No ACS check is needed. +DMKKT,,,NOT_COVERED,-,"Not testable: locks are per PARTID space. Non-secure ACS cannot verify locks in Secure, Realm, or Root spaces." +VTFQK,Yes,Yes,COVERED,-,No ACS check required: monitor locks may be separate or shared with partition locks. Both designs are permitted. +CTGKD,,,NOT_COVERED,-,"Not testable: monitor locks are per PARTID space. Non-secure ACS cannot verify locks in Secure, Realm, or Root spaces." +RDMVJ,Yes,Yes,COVERED,-,No ACS check required: implementation-defined MMRs are permitted above offset 0x3000. No mandatory ACS check. +KNNBY,Yes,Yes,COVERED,reg001.c,Indirect: reg001.c is used as a representative MPAM feature-page register access test. Reserved/unimplemented register locations are not exhaustively probed. +ZPWLC,Yes,Yes,COVERED,reg001.c,Indirect: reg001.c is used as a representative Non-secure feature-page access test. Other PA-space feature pages are not accessible to ACS. +DYDFT,Yes,Yes,COVERED,reg001.c,"Indirect: reg001.c is used as a representative Non-secure feature-page base access test. Secure, Realm, and Root bases cannot be validated from Non-secure ACS." +HXLMF,Yes,Yes,COVERED,-,No ACS check required: different feature-page base addresses are permitted and overlap avoidance is a recommendation. No mandatory ACS check. +QCYPH,,,NOT_COVERED,-,"Gap: feature-page alignment and containment are testable from platform data, but no current mapped test covers them." +FLWNK,Yes,Yes,COVERED,-,No ACS check required: non-MPAM MMR placement in the feature page is permitted only for trapped MMRs. No mandatory ACS check. +GTKCX,Yes,Yes,COVERED,reg001.c,Indirect: all SYS-MPAM MMR-based tests require the Non-secure MPAM feature page to exist. +DFBBW,,,NOT_COVERED,-,Not testable: secure feature page existence cannot be verified from Non-secure ACS execution. +FYTQL,,,NOT_COVERED,-,Not testable: realm and Root feature pages cannot be verified from Non-secure ACS execution. +KZBWG,Yes,Yes,COVERED,-,No ACS check required: rO MMR sharing across security states is permitted when contents match. ACS cannot and need not check sharing. +YCBKB,Yes,Yes,COVERED,"partition004.c, mem001.c",Indirect: PBM partitioning tests program CPBM/MBWPBM words using IDR widths and PBM offsets. +TVYHS,,,NOT_COVERED,-,"Gap: unused PBM bits being RES0 is testable, but no current mapped test covers it." +RJFKG,Yes,Yes,COVERED,"partition005.c, mem002.c","Indirect: fractional partitioning helpers program values using percentage minus one lsb, and tests validate resulting behavior." +FKNKB,Yes,Yes,COVERED,"partition006.c, feat001.c",Direct: tests program 100 percent controls and disable PARTIDs through MPAMCFG_DIS.PARTID. diff --git a/docs/mpam/arm_sys-mpam_testcase_checklist.json b/docs/mpam/arm_sys-mpam_testcase_checklist.json new file mode 100644 index 00000000..db67e6d2 --- /dev/null +++ b/docs/mpam/arm_sys-mpam_testcase_checklist.json @@ -0,0 +1,2582 @@ +{ + "metadata": { + "title": "SYS-MPAM Rule Coverage Checklist", + "architecture": "SYS-MPAM", + "rule_order": "SYS-MPAM architecture specification order", + "source": "SYS-MPAM architecture specification", + "total_rules": 213, + "csv_download_label": "Download SYS-MPAM testcase checklist CSV", + "status_order": [ + "COVERED", + "NOT_COVERED" + ], + "platforms": [ + "BM", + "UEFI" + ] + }, + "status_definitions": { + "COVERED": { + "meaning": "Rule is closed for ACS coverage: directly covered, indirectly covered, or no standalone ACS check is required. See Notes for the reason." + }, + "NOT_COVERED": { + "meaning": "Rule is not closed by ACS coverage. It is either not testable by ACS or is a coverage gap. See Notes for the reason." + } + }, + "rules": [ + { + "rule_id": "BDJXQ", + "status": "COVERED", + "tests": [ + "monitor001.c" + ], + "notes": "Indirect: monitor001 programs request PARTID and PMG and verifies monitor accounting distinguishes the labels.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DDGSM", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: MSC may implement zero or more resource controls. ACS checks controls only when discovered.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RBCMK", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: MSC may implement zero or more monitors. ACS checks monitors only when discovered.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CFXGZ", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Direct: reg001 checks MPAM version EXT bit behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FXVBB", + "status": "COVERED", + "tests": [ + "reg004.c" + ], + "notes": "Direct: reg004 checks MPAM-for-RME feature requirements.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LRZGD", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: different MPAM architecture versions may coexist. ACS validates each discovered MSC against its advertised version.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PBSTK", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: base memory behavior rules always apply. No separate SYS-MPAM ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KXMHB", + "status": "COVERED", + "tests": [ + "reg004.c" + ], + "notes": "Indirect: non-secure PARTID space is exercised by ACS. Secure, Realm, and Root spaces cannot be directly validated from Non-secure execution.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CZHSY", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot compare the same PARTID across Secure, Non-secure, Root, and Realm PARTID spaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RBWRS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot access all PARTID spaces to prove each PARTID scope is space-local.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QKQCF", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: Default PARTID 0 is architecturally defined; labeling non-MPAM requesters with it is permitted, not mandatory.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CZSZX", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot observe non-MPAM requester labeling to prove Default PMG 0 is used.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NVNHD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: requester-generation mechanism is system-wide. ACS cannot prove every PE, SMMU, GIC, and non-PE requester path.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SLJDR", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: non-PE requester-generated PARTID space, PARTID, and PMG values are not directly observable by ACS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VNVMD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: non-MPAM requester default/system-specific labeling is not directly controllable or observable by ACS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SJFGX", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: terminating completer has no downstream MPAM propagation to observe. No ACS runtime check is needed.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YPHLH", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: intermediate forwarding of MPAM information is fabric behavior. ACS cannot observe the downstream bundle directly.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RZCWR", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: buffered-request MPAM retention is internal. ACS cannot force or inspect a buffered request path.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MRWWK", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: conditional cache-internal storage rule. ACS checks observable controls and monitors when present.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XPPBS", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: cache partition tests exercise MSC response to request MPAM information.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CWTSC", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partition tests exercise per-PARTID control lookup from request MPAM information.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JWKJD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: cache-line MPAM metadata is internal. ACS cannot inspect the PARTID associated with each line.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SGBFN", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: cache eviction metadata is internal. ACS cannot prove PARTID preservation from inner to outer cache.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZTFBQ", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative simple MMR access test. It uses the common MSC discovery/configuration path, including integrated PE MSCs if discovered.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JGWSM", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative Non-secure MMR access test. Secure, Realm, and Root PA spaces are not directly accessible to ACS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LRNPR", + "status": "COVERED", + "tests": [ + "reg005.c" + ], + "notes": "Indirect: reg004/reg005 check visible MPAM-for-RME and four-space capability.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VBHPB", + "status": "COVERED", + "tests": [ + "reg004.c" + ], + "notes": "Indirect: reg004/reg005 cover visible PE/MSC capability; Non-secure traffic exercises Non-secure MPAM_SP propagation.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WZXPM", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative Non-secure MPAM access test. ACS cannot directly observe MPAM_NS signal propagation or Secure-side traffic.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CBBRW", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot generate Secure traffic or check reserved Secure PARTID-space encodings.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CNQCS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot observe 4-to-2 bridge reduction from Root/Realm MPAM_SP to MPAM_NS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "BHHCR", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot observe whether a 4-to-2 bridge uses static or dynamic reduction.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "BSLZQ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot observe 2-to-4 bridge expansion from MPAM_NS to MPAM_SP.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WBZST", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot prove bridge preservation of physical address space and PARTID space.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YWPPT", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: design statement for true two-space components. No separate ACS runtime check is needed.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "BNKHP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: mAP4SPTO2SP is Root PA-space only; Non-secure ACS cannot verify Root-only access.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KFDFD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: external mapping register is Root PA-space only; Non-secure ACS cannot verify Root-only access.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XRQHH", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot observe fixed MPAM_SP to MPAM_NS bridge signal mapping.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VKQKB", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot identify or control all non-MPAM components to prove they do not propagate MPAM information.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TTSLQ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS does not control SMMU-attached requester traffic or observe its PARTID-space use.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RGSJV", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: completer interface behavior. ACS cannot observe whether MPAM information was dropped before a non-MPAM completer.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MFRGP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: interconnect transport behavior. ACS cannot directly observe MPAM information on fabric links.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CYKPC", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: cache-line MPAM metadata is internal. ACS cannot inspect whether allocated lines store the request MPAM information.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KPNNZ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: cache eviction propagation behavior. ACS cannot observe MPAM metadata passed with evicted cache lines.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JXRZM", + "status": "COVERED", + "tests": [ + "monitor001.c" + ], + "notes": "Direct: CSUMON tests check cache-storage usage monitoring when implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RHYKB", + "status": "COVERED", + "tests": [ + "monitor001.c" + ], + "notes": "Direct: CSUMON PMG/PARTID filter tests check cache-storage accounting for matching criteria.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LQQJN", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: write-hit cache-line association is implementation-specific and cache-internal; ACS cannot observe the chosen association.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KBJPW", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: write-hit portion update is permitted but not required, so there is no mandatory ACS behavior to check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YBYPZ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: reset/default-state behavior. SYS-MPAM ACS does not need a runtime check unless MPAM controls are discovered after boot.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CNGYT", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Direct: cache partitioning tests use CSU measurement to validate capacity-based partitioning behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HHQWY", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Direct: RIS tests exercise resource/control discovery and RIS-based control or monitor selection.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WSXSL", + "status": "COVERED", + "tests": [ + "partition001.c", + "error008.c" + ], + "notes": "Direct: partitioning and RIS tests exercise common resource-control selection using PARTID and RIS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YQBMW", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Direct: RIS tests exercise resource-instance selection and RIS-based control/monitor behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YXZFG", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Indirect: RIS tests rely on discovered RIS values, but uniqueness is not the primary assertion.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DQNFB", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Indirect: RIS tests use RIS values in the 0..RIS_MAX range, but sparse assignment is not the primary assertion.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YGZYL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: common controls can only be inferred when advertised at RIS 0. If identical controls appear for all RIS values, ACS cannot prove whether they are common or per-resource.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PLZWM", + "status": "COVERED", + "tests": [ + "error009.c" + ], + "notes": "Indirect: error009 exercises RIS no-control behavior, which covers unsupported non-zero RIS paths for partition controls.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DNNTB", + "status": "COVERED", + "tests": [ + "error010.c" + ], + "notes": "Direct: monitor RIS tests use MSMON_CFG_MON_SEL.RIS to select resource-instance monitors.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LXXDB", + "status": "COVERED", + "tests": [ + "error010.c" + ], + "notes": "Indirect: monitor RIS tests exercise RIS selection and unsupported monitor RIS paths; unassociated-monitor RIS 0 is not separately asserted.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MRZLG", + "status": "COVERED", + "tests": [ + "error008.c", + "error010.c" + ], + "notes": "Indirect: RIS tests use RIS_MAX and undefined RIS paths, but do not directly assert every permitted RIS decode rule.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NPVVN", + "status": "COVERED", + "tests": [ + "error008.c", + "error009.c", + "error010.c", + "error011.c" + ], + "notes": "Direct: RIS error tests validate undefined RIS, no-control, and no-monitor selected-resource cases.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HSFKH", + "status": "COVERED", + "tests": [ + "error012.c" + ], + "notes": "Direct: error012 checks ID register HAS fields read zero and no ESR error for undefined RIS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XRHKL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: virtual PARTID resolution happens before the MSC. ACS cannot observe the pre-resolution virtual PARTID path.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GDMQZ", + "status": "COVERED", + "tests": [ + "reg005.c" + ], + "notes": "Direct: reg005 checks MSC four-space capability when MPAM for RME is supported.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MMXWZ", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative MMR access test using MPAMF_BASE_ns from ACPI/platform data. Secure, Realm, and Root base fields are not validated.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QFCTM", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: allows controls and monitors to differ by PA space. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CZMFT", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: defines when a resource can be partitioned. Actual controls are checked only when implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XDZGT", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: describes possible RIS support for multiple resources. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HLHYS", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: lists optional standard partitioning interfaces. ACS checks only implemented interfaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GVCBB", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partitioning tests check IDR support bits before exercising each advertised control.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KWGHQ", + "status": "COVERED", + "tests": [ + "partition001.c", + "mem001.c" + ], + "notes": "Indirect: CPOR and MBWPBM tests use portion/PBM width and allocation behavior, but do not directly assert every generic portion property.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TZWJG", + "status": "COVERED", + "tests": [ + "feat001.c" + ], + "notes": "Indirect: feat001 exercises PARTID enable/disable behavior; the global-to-MSC scope is not directly asserted.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VFJMZ", + "status": "COVERED", + "tests": [ + "feat001.c" + ], + "notes": "Direct: feat001 verifies that a disabled PARTID allocates no resource or receives the lowest priority.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WFQFS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: ACS cannot directly observe preserved hardware settings across PARTID disable/re-enable; behavior can only give indirect confidence.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GMCWW", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a direct test to disable and re-enable one PARTID, then verify the effect across all RIS values.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CSLHH", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a direct PARTID narrowing test that disables a request PARTID and verifies the enabled status controls request behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QFRFQ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: defines normal enabled-control behavior. Feature-specific tests cover the implemented controls.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RNSLZ", + "status": "COVERED", + "tests": [ + "reg006.c" + ], + "notes": "Direct: reg006 checks NFU is not implemented when PARTID narrowing is supported.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NJXHP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: boot/reset enable state across all PARTIDs and spaces is not directly testable after firmware handoff.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XPPGG", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Direct: partition001 checks cache portion partitioning.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZVTKX", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partition001 exercises PARTID-based cache portion allocation.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RLHRV", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partition001 programs CPOR through the generic portion-control model.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZRSRZ", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partition001 exercises CPBM permission bits through CPOR allocation behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WMPLL", + "status": "COVERED", + "tests": [ + "partition001.c" + ], + "notes": "Indirect: partition001 uses CPBM as the cache instance of the generic PBM model.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LPLMM", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: cache-line portion after CPBM change is internal, and both reallocation and retained misallocation are allowed.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "BDRCM", + "status": "COVERED", + "tests": [ + "partition004.c" + ], + "notes": "Direct: partition004 checks cache associativity partitioning.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZHBXH", + "status": "COVERED", + "tests": [ + "partition002.c" + ], + "notes": "Direct: partition002 checks cache maximum-capacity partitioning.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SWNLN", + "status": "COVERED", + "tests": [ + "partition005.c" + ], + "notes": "Indirect: partition005 compares CMAX with SOFTLIM disabled/enabled, but does not directly prove unused capacity cannot be used above CMAX.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VZBFH", + "status": "COVERED", + "tests": [ + "partition005.c" + ], + "notes": "Direct: partition005 checks CMAX soft-limit behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CXZDR", + "status": "COVERED", + "tests": [ + "partition006.c" + ], + "notes": "Direct: partition006 checks CMIN allocation-priority behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FRTVY", + "status": "COVERED", + "tests": [ + "partition006.c" + ], + "notes": "Indirect: feat001, partition005, and partition006 exercise priority inputs, but not as a standalone priority table check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DPZKC", + "status": "COVERED", + "tests": [ + "partition006.c" + ], + "notes": "Indirect: cache partition tests exercise allocation behavior, but do not directly assert each candidate-selection step.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DKYDB", + "status": "COVERED", + "tests": [ + "mem001.c" + ], + "notes": "Direct: mem001 configures MBWPBM portions and validates bandwidth partition behavior with MBWU counters.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GYMDB", + "status": "COVERED", + "tests": [ + "mem001.c" + ], + "notes": "Direct: mem001 programs BWPBM bits through MBWPBM configuration and validates permitted bandwidth behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CFHQL", + "status": "COVERED", + "tests": [ + "mem001.c" + ], + "notes": "Indirect: mem001 validates BWPBM behavior as a PBM-style bandwidth portion control.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HVRZS", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: lists optional bandwidth partitioning methods. ACS checks only methods that are implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WKZBJ", + "status": "COVERED", + "tests": [ + "mem002.c", + "mem003.c" + ], + "notes": "Indirect: mem002 and mem003 validate MBWMIN/MBWMAX fraction behavior, but not every bandwidth control type in the table.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "BPRDL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: end-to-end bandwidth guarantee across concatenated MSCs is system-performance behavior that ACS cannot prove reliably.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WRXBV", + "status": "COVERED", + "tests": [ + "mem002.c" + ], + "notes": "Direct: mem002 programs MBWMIN under contention and validates bandwidth behavior with MBWU counters.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NWVFK", + "status": "COVERED", + "tests": [ + "mem003.c" + ], + "notes": "Direct: mem003 programs MBWMAX hard limits and validates bandwidth behavior with MBWU counters.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PKRGZ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a combined MBWMIN+MBWMAX test; current tests validate each control separately.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VWHYW", + "status": "COVERED", + "tests": [ + "mem003.c" + ], + "notes": "Indirect: mem002 and mem003 validate MBWMIN/MBWMAX behavior that relies on accounting-window tracking.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PWSWQ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: accounting-window carry-over is internal and implementation-dependent; ACS cannot reliably prove unused bandwidth does not accumulate.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XSYFH", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: fixed accounting-window state is internal; ACS cannot reliably prove history clear and new-window behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZQXQL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: priority partitioning for same-preference conflicts is testable, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CMZNL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: moving accounting-window history aging is internal; ACS cannot reliably prove request aging and removal behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PXSBS", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: allows implementation-defined bandwidth tracking methods. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZDTLN", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: defines proportional stride as a generic proportional-control instance. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZFCRG", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: hAS_PROP advertisement is testable through MPAMF_MBW_IDR, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TKBDC", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a combined proportional-stride + MBWMAX test; current tests cover MBWMAX only.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MSPZM", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: different priorities per MSC are testable through priority controls, but no current mapped test covers them.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JJKQP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: upstream QoS priority arrival is fabric behavior. ACS cannot observe incoming interconnect priority signals.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NGDBL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: priority override affects internal MSC operation and downstream transport priority; ACS cannot directly observe it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MQRPH", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: internal priority partitioning is optional even when downstream priority exists. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RZDSR", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: downstream priority partitioning is optional even when internal priority exists. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MBNHC", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: response priority is downstream-to-upstream fabric behavior. ACS cannot directly observe response priority preservation.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JPLMZ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: implementation-defined controls cannot be interpreted generically by ACS. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DQTTD", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: PARTID narrowing support is optional. ACS checks narrowing behavior only if implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RNWBS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: PARTID narrowing coverage still needs dedicated work; no current test proves this behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GFYDF", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: iNTPARTID mapping programming is testable when narrowing exists, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WCQKV", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: defines monitor types. ACS checks monitors only when the corresponding monitor type is implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZGGMX", + "status": "COVERED", + "tests": [ + "monitor001.c" + ], + "notes": "Indirect: PARTID-based monitor tests use request PARTID filters; narrowing-specific behavior is not directly proven.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TMCXJ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: top-level monitor RIS 0 access is testable, but no current mapped monitor test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YFMQP", + "status": "COVERED", + "tests": [ + "mem001.c" + ], + "notes": "Direct: MBWU tests count payload bytes during memory workloads using MBWU monitor filters.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DLSGF", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: mBWU capture-event behavior is testable if capture registers exist, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WHJQG", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: MBWU overflow tests prefill the counter near maximum and verify overflow behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VLSJS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: no current ACS test explicitly verifies that MBWU_L VALUE is unscaled.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RYRQJ", + "status": "COVERED", + "tests": [ + "intr004.c" + ], + "notes": "Direct: intr004 prefills MBWU_L near maximum and verifies long-counter overflow status/interrupt behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QGXSZ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: no current ACS test triggers a CSU capture event; reg003 only rejects prohibited overflow-capture capability.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VJDKF", + "status": "COVERED", + "tests": [ + "monitor001.c", + "mem001.c" + ], + "notes": "Indirect: CSU and MBWU monitor tests read monitor VALUE only when NRDY is clear; no standalone structural check covers every monitor instance.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DSCQB", + "status": "COVERED", + "tests": [ + "monitor005.c", + "monitor008.c" + ], + "notes": "Indirect: MBWU tests verify VALUE advances/resumes and CSU tests read/write VALUE; no single test covers all VALUE-field behaviors.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FWCFZ", + "status": "COVERED", + "tests": [ + "monitor008.c" + ], + "notes": "Direct: monitor008 writes MBWU VALUE to zero and verifies the counter resumes advancing after new traffic.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PVNHR", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: overflow tests write MBWU VALUE near maximum and verify hardware traffic advances the counter.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KCWDZ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: monitor registers are permitted to be RO. No check is needed unless RW behavior is advertised.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XLWYW", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: rW monitor reprogramming without disable is permitted. No mandatory ACS behavior to check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GKWNB", + "status": "COVERED", + "tests": [ + "monitor001.c" + ], + "notes": "Indirect: CSU monitor tests reprogram PMG/PARTID criteria on the same monitor and continue reading VALUE after new traffic.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LRTGP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: nRDY=1 after settings update can be too transient to observe reliably in ACS execution.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NXKSF", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: MBWU monitor tests fail if the monitor remains not-ready after update/wait paths.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FVFYC", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: automatic NRDY clear is not required for event monitors. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZTXDS", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: software-defined NRDY use is permitted when automatic update is absent. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VBZTW", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: MBWU monitor tests wait MAX_NRDY_USEC and fail if NRDY remains set when the value is read.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FZHDC", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a capture-event test that reads the capture register NRDY copy and verifies monitor NRDY resets to 0 after capture.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YFVPY", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs capture-event tests across monitor instances and capture registers; current tests only check prohibited capture capability.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NKTBN", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies immediate capture completion.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NWKJR", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies external capture distribution.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SQSMV", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: capture reset after copy is permitted but not required. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WQJKV", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: MBWU overflow tests drive VALUE past max and verify OFLOW_STATUS or OFLOW_STATUS_L is set.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XZXVK", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Indirect: monitor007 verifies post-overflow counter freeze/advance behavior, but does not directly assert the wrapped VALUE.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NDMMK", + "status": "COVERED", + "tests": [ + "monitor008.c" + ], + "notes": "Direct: monitor008 clears OFLOW_STATUS through MSMON_CFG_MBWU_CTL and fails if the status remains set.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VBBTL", + "status": "COVERED", + "tests": [ + "monitor005.c", + "monitor006.c" + ], + "notes": "Direct: monitor tests disable the monitor, update MSMON_CFG control/value state, and verify the written state is usable.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XSTRM", + "status": "COVERED", + "tests": [ + "monitor007.c" + ], + "notes": "Direct: monitor007 checks configurable monitor overflow behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JCNST", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies linked capture-on-overflow behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DFWFP", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies capture events stay local to one MSC.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GNQFY", + "status": "COVERED", + "tests": [ + "monitor008.c" + ], + "notes": "Direct: monitor008 checks overflow status reset when monitor VALUE is written.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MGGJW", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies external capture distribution to all PARTID spaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HXNGD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; no current ACS test verifies local capture distribution across address spaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RPGBQ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: overflow linkage event is permitted for monitor types without capture-on-overflow. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MTGGZ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: capture feature coverage is pending; current OFLOW_FRZ test does not verify freeze caused by a capture event.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DYNFP", + "status": "COVERED", + "tests": [ + "error014.c" + ], + "notes": "Indirect: error014 triggers a second MPAM error after the first and verifies ESR updates, showing continued MSC error handling.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WHSLQ", + "status": "COVERED", + "tests": [ + "error001.c", + "error003.c", + "error005.c", + "error008.c", + "error010.c", + "error014.c" + ], + "notes": "Indirect: error tests validate multiple MPAMF_ESR ERRCODE table entries and selected captured fields, but not every table row or security-state case.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GVBGS", + "status": "COVERED", + "tests": [ + "error014.c" + ], + "notes": "Direct: error014 generates a second MPAM error before clearing ESR and verifies ERRCODE updates.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QBKDG", + "status": "COVERED", + "tests": [ + "error013.c" + ], + "notes": "Direct: error013 checks MPAMF_ESR.RIS reports the selector RIS that caused the error.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DLSCZ", + "status": "COVERED", + "tests": [ + "error001.c" + ], + "notes": "Direct: error001 checks out-of-range PARTID_SEL error behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZWRQW", + "status": "COVERED", + "tests": [ + "error003.c" + ], + "notes": "Direct: error003 checks MPAMCFG access behavior with out-of-range PARTID_SEL.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VKKDP", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Direct: error008 checks undefined RIS handling in MPAMCFG_PART_SEL.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XTQZR", + "status": "COVERED", + "tests": [ + "error012.c", + "error013.c" + ], + "notes": "Direct: error012 reads MPAMF_IDR with undefined RIS, and error013 reads MPAMCFG after programming undefined RIS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XDCDL", + "status": "COVERED", + "tests": [ + "error008.c" + ], + "notes": "Direct: error008 checks undefined MPAMCFG_PART_SEL.RIS access and accepts ERRCODE 8 or RAZ/WI behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JMLNM", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: read value is architecturally UNKNOWN for these error cases, so ACS cannot validate a required value.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "XMLDN", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: resulting control setting is architecturally UNKNOWN for these write-error cases, so ACS cannot validate a required value.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VMTBP", + "status": "COVERED", + "tests": [ + "error005.c" + ], + "notes": "Direct: error005 checks out-of-range monitor selector error behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "WXKWK", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: read value is architecturally UNKNOWN for out-of-range MON_SEL, so ACS cannot validate a required value.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MGXDK", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: post-write behavior is implementation-defined with UNKNOWN selector or WI, so ACS cannot validate one required result.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HJRZC", + "status": "COVERED", + "tests": [ + "error010.c" + ], + "notes": "Direct: error010 checks undefined RIS handling in MSMON_CFG_MON_SEL.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SQTSJ", + "status": "COVERED", + "tests": [ + "error010.c" + ], + "notes": "Direct: error010 validates ERRCODE 10 for undefined MSMON_CFG_MON_SEL.RIS; read value is UNKNOWN and not directly assertable.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VZWYW", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: needs a test that programs undefined MSMON_CFG_MON_SEL.RIS, then writes another MSMON register and checks ERRCODE 10 or allowed write behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PNPQQ", + "status": "COVERED", + "tests": [ + "error001.c", + "error003.c", + "error005.c" + ], + "notes": "Indirect: implemented error tests exercise required reporting for selected supported error conditions.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "SJFMB", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: hAS_ESR may be zero when no reportable errors exist. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VYLZC", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: defines selector types used by later error rules. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QBQJG", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: selector truncation behavior is permitted. ACS only checks invalid selector reporting when required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PFNBV", + "status": "COVERED", + "tests": [ + "error001.c" + ], + "notes": "Indirect: out-of-range selector tests indirectly exercise invalid selector detection.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CZZZK", + "status": "COVERED", + "tests": [ + "error007.c" + ], + "notes": "Direct: error007 checks Unexpected INTERNAL error reporting when PARTID narrowing is supported.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HVNKJ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: lists possible MPAM interrupt sources. ACS checks only implemented interrupt behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TMMMD", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: four-space MSC choice of Secure or Non-secure error interrupt is permitted. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QDSPY", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: applies when no reportable error can occur or detection is optional. No standalone ACS check is required.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "PPJSM", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: error interrupt type may be level-sensitive or edge-triggered. ACS checks the implemented type.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GLPPK", + "status": "COVERED", + "tests": [ + "intr001.c" + ], + "notes": "Direct: intr001 checks level-sensitive error interrupt behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "NRGQD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: level-sensitive error interrupt must not use MSI. This is testable if interrupt type is discoverable, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KVGWS", + "status": "COVERED", + "tests": [ + "intr002.c" + ], + "notes": "Direct: intr002 checks edge-triggered error interrupt behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KVHTZ", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: mSI error interrupt requiring edge-triggered behavior is testable, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZRDMM", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: overflow interrupt support is optional. ACS checks overflow interrupts only if implemented.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YLCVK", + "status": "COVERED", + "tests": [ + "intr003.c" + ], + "notes": "Direct: intr003 checks overflow interrupt generation conditions.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YJCDR", + "status": "COVERED", + "tests": [ + "intr005.c" + ], + "notes": "Direct: intr005 checks MSI overflow interrupt edge-triggered requirement.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YVSNK", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: mSMON_OFLOW_SR summary behavior is testable if implemented, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "JLYJJ", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative simple MMR access test. It discovers MSCs and reads memory-mapped MPAM registers.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "MBDJF", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: 32-bit MMR single-copy atomicity is a bus atomicity property that ACS cannot prove reliably.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "LVCGQ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: greater-than-32-bit MMR atomicity is not required. No ACS check is needed.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DMKKT", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: locks are per PARTID space. Non-secure ACS cannot verify locks in Secure, Realm, or Root spaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "VTFQK", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: monitor locks may be separate or shared with partition locks. Both designs are permitted.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "CTGKD", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: monitor locks are per PARTID space. Non-secure ACS cannot verify locks in Secure, Realm, or Root spaces.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RDMVJ", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: implementation-defined MMRs are permitted above offset 0x3000. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KNNBY", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative MPAM feature-page register access test. Reserved/unimplemented register locations are not exhaustively probed.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "ZPWLC", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative Non-secure feature-page access test. Other PA-space feature pages are not accessible to ACS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DYDFT", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: reg001.c is used as a representative Non-secure feature-page base access test. Secure, Realm, and Root bases cannot be validated from Non-secure ACS.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "HXLMF", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: different feature-page base addresses are permitted and overlap avoidance is a recommendation. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "QCYPH", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: feature-page alignment and containment are testable from platform data, but no current mapped test covers them.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FLWNK", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: non-MPAM MMR placement in the feature page is permitted only for trapped MMRs. No mandatory ACS check.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "GTKCX", + "status": "COVERED", + "tests": [ + "reg001.c" + ], + "notes": "Indirect: all SYS-MPAM MMR-based tests require the Non-secure MPAM feature page to exist.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "DFBBW", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: secure feature page existence cannot be verified from Non-secure ACS execution.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FYTQL", + "status": "NOT_COVERED", + "tests": [], + "notes": "Not testable: realm and Root feature pages cannot be verified from Non-secure ACS execution.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "KZBWG", + "status": "COVERED", + "tests": [], + "notes": "No ACS check required: rO MMR sharing across security states is permitted when contents match. ACS cannot and need not check sharing.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "YCBKB", + "status": "COVERED", + "tests": [ + "partition004.c", + "mem001.c" + ], + "notes": "Indirect: PBM partitioning tests program CPBM/MBWPBM words using IDR widths and PBM offsets.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "TVYHS", + "status": "NOT_COVERED", + "tests": [], + "notes": "Gap: unused PBM bits being RES0 is testable, but no current mapped test covers it.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "RJFKG", + "status": "COVERED", + "tests": [ + "partition005.c", + "mem002.c" + ], + "notes": "Indirect: fractional partitioning helpers program values using percentage minus one lsb, and tests validate resulting behavior.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + }, + { + "rule_id": "FKNKB", + "status": "COVERED", + "tests": [ + "partition006.c", + "feat001.c" + ], + "notes": "Direct: tests program 100 percent controls and disable PARTIDs through MPAMCFG_DIS.PARTID.", + "sub_rules": [], + "platforms": [ + "BM", + "UEFI" + ] + } + ] +} diff --git a/docs/mpam/arm_sys-mpam_testcase_checklist.md b/docs/mpam/arm_sys-mpam_testcase_checklist.md new file mode 100644 index 00000000..cefec336 --- /dev/null +++ b/docs/mpam/arm_sys-mpam_testcase_checklist.md @@ -0,0 +1,63 @@ +# SYS-MPAM Rule Coverage Checklist + +This document describes the SYS-MPAM rule coverage checklist and status categories. +The coverage matrix itself is maintained in JSON form and generated as CSV so it +can be downloaded, filtered, and reviewed without duplicating the full table here. + +## Current Summary + +| Status | Count | +| --- | ---: | +| `COVERED` | 138 | +| `NOT_COVERED` | 75 | +| `TOTAL` | 213 | + +## Platform Information + +Platform coverage is tracked per rule in the generated CSV. Platform columns are left blank when the rule is not covered. + +## Coverage Matrix + +The full checklist is available here: + +[Download SYS-MPAM testcase checklist CSV](arm_sys-mpam_testcase_checklist.csv) + +Gitiles may display the CSV as plain text. Download the file and open it in +Excel, LibreOffice, or another spreadsheet tool for filtering and offline review. + +The CSV contains these columns: + +| Column | Description | +| --- | --- | +| `Specification Rule ID` | Architecture rule ID. | +| `BM` | Whether ACS coverage exists for this platform; blank when not covered. | +| `UEFI` | Whether ACS coverage exists for this platform; blank when not covered. | +| `Status` | Current ACS coverage classification. | +| `Tests` | Direct ACS test file or indirect coverage source. | +| `Notes` | Short reasoning for the classification. | + +## Status Definitions + +| Status | Meaning | +| --- | --- | +| `COVERED` | Rule is closed for ACS coverage: directly covered, indirectly covered, or no standalone ACS check is required. See Notes for the reason. | +| `NOT_COVERED` | Rule is not closed by ACS coverage. It is either not testable by ACS or is a coverage gap. See Notes for the reason. | + +## Maintenance + +Update `arm_sys-mpam_testcase_checklist.json` when rule coverage changes, then regenerate this +Markdown file and the CSV with: + +```bash +python3 tools/scripts/generate_rule_checklist.py --json docs/mpam/arm_sys-mpam_testcase_checklist.json +``` + +To choose explicit output paths: + +```bash +python3 tools/scripts/generate_rule_checklist.py --json docs/mpam/arm_sys-mpam_testcase_checklist.json --md docs/mpam/arm_sys-mpam_testcase_checklist.md --csv docs/mpam/arm_sys-mpam_testcase_checklist.csv +``` + +Direct executable mappings must still be represented in `rule_metadata.c`. +Coverage detail is captured in `Notes` using prefixes such as `Direct:`, +`Indirect:`, `No ACS check required:`, `Not testable:`, and `Gap:`. diff --git a/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c b/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c index 2644624c..7f6d7518 100644 --- a/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c +++ b/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c @@ -20,31 +20,6 @@ #include "platform_override_struct.h" #include "rule_based_execution_enum.h" -/* - * MPAM-only, non-rulebase selection arrays. - * - * To run specific modules: - * - Put module base numbers in g_module_array (see val/include/bsa_acs_common.h). - * - Example: {300} runs only MPAM memory tests (ACS_MPAM_MEMORY_TEST_NUM_BASE). - * - * To run specific tests: - * - Put test numbers in g_test_array (see test_pool//test.c). - * - Example: {101} runs only the first MPAM cache test (ACS_MPAM_CACHE_TEST_NUM_BASE + 1). - * - * To skip tests/modules: - * - Put test numbers or module bases in g_skip_array. - * - Tests run = g_test_array + g_module_array - entries in g_skip_array. - */ -#ifndef COMPILE_RB_EXE -uint32_t g_skip_array[] = {}; -uint32_t g_test_array[] = {}; -uint32_t g_module_array[] = {}; - -const uint32_t g_skip_array_len = sizeof(g_skip_array) / sizeof(g_skip_array[0]); -const uint32_t g_test_array_len = sizeof(g_test_array) / sizeof(g_test_array[0]); -const uint32_t g_module_array_len = sizeof(g_module_array) / sizeof(g_module_array[0]); -#endif - /* Following global variables can be edited by user before compilation to pass hints to framework as well as run compliance against subset of rules. diff --git a/patches/edk2_mpam.patch b/patches/edk2_mpam.patch index 20c3d818..a8f0db57 100644 --- a/patches/edk2_mpam.patch +++ b/patches/edk2_mpam.patch @@ -4,7 +4,7 @@ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf -+ ValLib|ShellPkg/Application/sysarch-acs/val/ValLib.inf ++ ValLib|ShellPkg/Application/sysarch-acs/val/ValLibRB.inf + PalLib|ShellPkg/Application/sysarch-acs/pal/uefi_acpi/PalLib.inf [PcdsFixedAtBuild] @@ -17,3 +17,9 @@ ShellPkg/Application/Shell/Shell.inf { +@@ -157,4 +160,4 @@ + ShellPkg/DynamicCommand/VariablePolicyDynamicCommand/VariablePolicyApp.inf + + [BuildOptions] +- *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES ++ *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES -D SYS_MPAM_UEFI_BUILD diff --git a/test_pool/mpam/error001.c b/test_pool/mpam/error001.c index 365fb21d..1e6b7bc3 100644 --- a/test_pool/mpam/error001.c +++ b/test_pool/mpam/error001.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 1 #define TEST_DESC "Check MSC PARTID selection range error" -#define TEST_RULE "" +#define TEST_RULE "DLSCZ" static void payload(void) { @@ -91,12 +91,14 @@ static void payload(void) return; } -uint32_t error001_entry(void) +uint32_t error001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error002.c b/test_pool/mpam/error002.c index e1c9ac35..9adb3e6e 100644 --- a/test_pool/mpam/error002.c +++ b/test_pool/mpam/error002.c @@ -103,12 +103,13 @@ void payload(void) return; } -uint32_t error002_entry(void) +uint32_t error002_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error003.c b/test_pool/mpam/error003.c index 50067450..4d25884e 100644 --- a/test_pool/mpam/error003.c +++ b/test_pool/mpam/error003.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 3 #define TEST_DESC "Check MSMON ConfigID out-of-range Err " -#define TEST_RULE "" +#define TEST_RULE "ZWRQW" static void payload(void) @@ -44,6 +44,8 @@ void payload(void) for (index = 0; index < total_nodes; index++) { + mon_count = 0; + if (!val_mpam_msc_supports_esr(index)) { val_print(DEBUG, "\n MSC index %d does not support ESR", index); continue; @@ -58,18 +60,16 @@ void payload(void) return; } - /* Read the number of monitors implemented in this MSC */ + /* Use the count for the monitor type selected by the error helper. */ if (val_mpam_msc_supports_mon(index)) { if (val_mpam_supports_csumon(index)) { - mon_count += val_mpam_get_csumon_count(index); + mon_count = val_mpam_get_csumon_count(index); val_print(DEBUG, "\n MSC implements %d CSU Monitors", mon_count); - } - - if (val_mpam_msc_supports_mbwumon(index)) { - mon_count += val_mpam_get_mbwumon_count(index); + } else if (val_mpam_msc_supports_mbwumon(index)) { + mon_count = val_mpam_get_mbwumon_count(index); val_print(DEBUG, - "\n MSC implements %d MBWU Monitors", val_mpam_get_mbwumon_count(index)); + "\n MSC implements %d MBWU Monitors", mon_count); } } @@ -110,12 +110,14 @@ void payload(void) return; } -uint32_t error003_entry(void) +uint32_t error003_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error004.c b/test_pool/mpam/error004.c index a4ca9d1a..5491da37 100644 --- a/test_pool/mpam/error004.c +++ b/test_pool/mpam/error004.c @@ -103,12 +103,13 @@ void payload(void) return; } -uint32_t error004_entry(void) +uint32_t error004_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error005.c b/test_pool/mpam/error005.c index 88d2e1a2..0dce3439 100644 --- a/test_pool/mpam/error005.c +++ b/test_pool/mpam/error005.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 5 #define TEST_DESC "Check MSC MONITOR selection range Err " -#define TEST_RULE "" +#define TEST_RULE "VMTBP" static void payload(void) @@ -116,12 +116,14 @@ void payload(void) return; } -uint32_t error005_entry(void) +uint32_t error005_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error006.c b/test_pool/mpam/error006.c index af0711e7..5531809d 100644 --- a/test_pool/mpam/error006.c +++ b/test_pool/mpam/error006.c @@ -112,12 +112,13 @@ void payload(void) return; } -uint32_t error006_entry(void) +uint32_t error006_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error007.c b/test_pool/mpam/error007.c index 174b5ab0..023bfc4b 100644 --- a/test_pool/mpam/error007.c +++ b/test_pool/mpam/error007.c @@ -110,12 +110,14 @@ void payload(void) return; } -uint32_t error007_entry(void) +uint32_t +error007_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error008.c b/test_pool/mpam/error008.c index 625881e1..8daac1f4 100644 --- a/test_pool/mpam/error008.c +++ b/test_pool/mpam/error008.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 8 #define TEST_DESC "Check Undef RIS MPAMCFG_PART_SEL error" -#define TEST_RULE "" +#define TEST_RULE "VKKDP" static uint32_t max_ris_index; @@ -45,7 +45,7 @@ check_for_raz_wi(uint32_t msc_index, uint32_t reg_offset) data = BITFIELD_SET(PART_SEL_PARTID_SEL, 0x10) | BITFIELD_SET(PART_SEL_RIS, (max_ris_index + 1)); val_mpam_mmr_write(msc_index, reg_offset, data); - val_mpam_mmr_read(msc_index, reg_offset); + reg_value = val_mpam_mmr_read(msc_index, reg_offset); if (reg_value != 0x00) return ACS_STATUS_FAIL; @@ -114,17 +114,21 @@ void payload(void) esr_errcode = val_mpam_msc_get_errcode(msc_index); val_print(DEBUG, "\n Error code read is %llx", esr_errcode); - if (esr_errcode != ESR_ERRCODE_UNDEF_RIS_PART_SEL) - { - val_print(ERROR, "\n Expected errcode: %d", - ESR_ERRCODE_UNDEF_RIS_PART_SEL); + status = check_for_raz_wi(msc_index, REG_MPAMCFG_PART_SEL); + if (status == ACS_STATUS_FAIL) { + val_print(ERROR, + "\n MPAMCFG_PART_SEL is not RAZ/WI with out-of-range RIS programmed"); + test_fail++; + } + + if ((esr_errcode != ESR_ERRCODE_UNDEF_RIS_PART_SEL) && + (esr_errcode != ESR_ERRCODE_NO_ERROR)) { + val_print(ERROR, "\n Expected errcode: %d or no error", + ESR_ERRCODE_UNDEF_RIS_PART_SEL); val_print(ERROR, "\n Actual errcode: %d", esr_errcode); - status = check_for_raz_wi(msc_index, REG_MPAMCFG_PART_SEL); - if (status == ACS_STATUS_FAIL) { - val_print(ERROR, - "\n MPAMCFG_PART_SEL is not RAZ/WI with out-of-range RIS programmed"); - test_fail++; - } + test_fail++; + } else if (esr_errcode == ESR_ERRCODE_NO_ERROR) { + val_print(DEBUG, "\n Error not reported; permitted RAZ/WI behavior observed"); } /* Restore Error Control Register original settings */ @@ -140,12 +144,14 @@ void payload(void) return; } -uint32_t error008_entry(void) +uint32_t error008_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error009.c b/test_pool/mpam/error009.c index e00cc05e..28993eee 100644 --- a/test_pool/mpam/error009.c +++ b/test_pool/mpam/error009.c @@ -44,7 +44,7 @@ check_for_raz_wi(uint32_t reg_offset) /* Check if register ignores write */ val_mpam_mmr_write(msc_index, reg_offset, PSUEDO_REG_VALUE); - val_mpam_mmr_read(msc_index, reg_offset); + reg_value = val_mpam_mmr_read(msc_index, reg_offset); if (reg_value != 0x00) return ACS_STATUS_FAIL; @@ -56,7 +56,7 @@ uint32_t configure_partitioning_reg(uint32_t reg_offset) { uint32_t esr_errcode; - uint32_t status; + uint32_t status = ACS_STATUS_PASS; /* Write 0xFFFF to the unimplemented partitioning register of the MSC's resource */ val_mpam_mmr_write(msc_index, reg_offset, PSUEDO_REG_VALUE); @@ -71,13 +71,17 @@ configure_partitioning_reg(uint32_t reg_offset) esr_errcode = val_mpam_msc_get_errcode(msc_index); val_print(DEBUG, "\n Error code read is %llx", esr_errcode); - if (esr_errcode != ESR_ERRCODE_RIS_NO_CTRL) - { - val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_CTRL); - val_print(ERROR, "\n Actual errcode: %d", esr_errcode); + status = check_for_raz_wi(reg_offset); + if (status == ACS_STATUS_FAIL) + val_print(ERROR, "\n Partitioning register is not RAZ/WI"); - /* Check for RAZ/ WI*/ - status = check_for_raz_wi(reg_offset); + if ((esr_errcode != ESR_ERRCODE_RIS_NO_CTRL) && + (esr_errcode != ESR_ERRCODE_NO_ERROR)) { + val_print(ERROR, "\n Expected errcode: %d or no error", ESR_ERRCODE_RIS_NO_CTRL); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); + status = ACS_STATUS_FAIL; + } else if (esr_errcode == ESR_ERRCODE_NO_ERROR) { + val_print(DEBUG, "\n Error not reported; permitted RAZ/WI behavior observed"); } return status; @@ -190,12 +194,14 @@ void payload(void) return; } -uint32_t error009_entry(void) +uint32_t +error009_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error010.c b/test_pool/mpam/error010.c index 7309e1a8..134a3c85 100644 --- a/test_pool/mpam/error010.c +++ b/test_pool/mpam/error010.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 10 #define TEST_DESC "Check Undef RIS MSMON_CFG_MON_SEL Err " -#define TEST_RULE "" +#define TEST_RULE "HJRZC" static uint32_t max_ris_index; @@ -45,7 +45,7 @@ check_for_raz_wi(uint32_t msc_index, uint32_t reg_offset) data = BITFIELD_SET(MON_SEL_MON_SEL, 0x10) | BITFIELD_SET(MON_SEL_RIS, (max_ris_index + 1)); val_mpam_mmr_write(msc_index, reg_offset, data); - val_mpam_mmr_read(msc_index, reg_offset); + reg_value = val_mpam_mmr_read(msc_index, reg_offset); if (reg_value != 0x00) return ACS_STATUS_FAIL; @@ -119,17 +119,21 @@ void payload(void) esr_errcode = val_mpam_msc_get_errcode(msc_index); val_print(DEBUG, "\n Error code read is %llx", esr_errcode); - if (esr_errcode != ESR_ERRCODE_UNDEF_RIS_MON_SEL) - { - val_print(ERROR, "\n Expected errcode: %d", - ESR_ERRCODE_UNDEF_RIS_MON_SEL); + status = check_for_raz_wi(msc_index, REG_MSMON_CFG_MON_SEL); + if (status == ACS_STATUS_FAIL) { + val_print(ERROR, + "\n MSMON_CFG_MON_SEL is not RAZ/WI with out-of-range RIS programmed"); + test_fail++; + } + + if ((esr_errcode != ESR_ERRCODE_UNDEF_RIS_MON_SEL) && + (esr_errcode != ESR_ERRCODE_NO_ERROR)) { + val_print(ERROR, "\n Expected errcode: %d or no error", + ESR_ERRCODE_UNDEF_RIS_MON_SEL); val_print(ERROR, "\n Actual errcode: %d", esr_errcode); - status = check_for_raz_wi(msc_index, REG_MSMON_CFG_MON_SEL); - if (status == ACS_STATUS_FAIL) { - val_print(ERROR, - "\n MSMON_CFG_MON_SEL is not RAZ/WI with out-of-range RIS programmed"); - test_fail++; - } + test_fail++; + } else if (esr_errcode == ESR_ERRCODE_NO_ERROR) { + val_print(DEBUG, "\n Error not reported; permitted RAZ/WI behavior observed"); } /* Restore Error Control Register original settings */ @@ -145,12 +149,14 @@ void payload(void) return; } -uint32_t error010_entry(void) +uint32_t error010_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error011.c b/test_pool/mpam/error011.c index 2920017f..5b49bff6 100644 --- a/test_pool/mpam/error011.c +++ b/test_pool/mpam/error011.c @@ -44,7 +44,7 @@ check_for_raz_wi(uint32_t reg_offset) /* Check if register ignores write */ val_mpam_mmr_write(msc_index, reg_offset, PSUEDO_REG_VALUE); - val_mpam_mmr_read(msc_index, reg_offset); + reg_value = val_mpam_mmr_read(msc_index, reg_offset); if (reg_value != 0x00) return ACS_STATUS_FAIL; @@ -56,7 +56,7 @@ uint32_t configure_monitoring_reg(uint32_t reg_offset) { uint32_t esr_errcode; - uint32_t status; + uint32_t status = ACS_STATUS_PASS; /* Write 0xFFFF to the unimplemented monitoring register of the MSC's resource */ val_mpam_mmr_write(msc_index, reg_offset, PSUEDO_REG_VALUE); @@ -71,13 +71,17 @@ configure_monitoring_reg(uint32_t reg_offset) esr_errcode = val_mpam_msc_get_errcode(msc_index); val_print(DEBUG, "\n Error code read is %llx", esr_errcode); - if (esr_errcode != ESR_ERRCODE_RIS_NO_MON) - { - val_print(ERROR, "\n Expected errcode: %d", ESR_ERRCODE_RIS_NO_MON); - val_print(ERROR, "\n Actual errcode: %d", esr_errcode); + status = check_for_raz_wi(reg_offset); + if (status == ACS_STATUS_FAIL) + val_print(ERROR, "\n Monitoring register is not RAZ/WI"); - /* Check for RAZ/ WI*/ - status = check_for_raz_wi(reg_offset); + if ((esr_errcode != ESR_ERRCODE_RIS_NO_MON) && + (esr_errcode != ESR_ERRCODE_NO_ERROR)) { + val_print(ERROR, "\n Expected errcode: %d or no error", ESR_ERRCODE_RIS_NO_MON); + val_print(ERROR, "\n Actual errcode: %d", esr_errcode); + status = ACS_STATUS_FAIL; + } else if (esr_errcode == ESR_ERRCODE_NO_ERROR) { + val_print(DEBUG, "\n Error not reported; permitted RAZ/WI behavior observed"); } return status; @@ -185,12 +189,14 @@ void payload(void) return; } -uint32_t error011_entry(void) +uint32_t +error011_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error012.c b/test_pool/mpam/error012.c index e08fc852..a2f540cd 100644 --- a/test_pool/mpam/error012.c +++ b/test_pool/mpam/error012.c @@ -130,12 +130,14 @@ void payload(void) return; } -uint32_t error012_entry(void) +uint32_t +error012_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error013.c b/test_pool/mpam/error013.c index 964c83b2..433f02ee 100644 --- a/test_pool/mpam/error013.c +++ b/test_pool/mpam/error013.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 16 #define TEST_DESC "Check MPAMF_ESR.RIS field correctness " -#define TEST_RULE "" +#define TEST_RULE "QBKDG" static void payload(void) @@ -171,12 +171,14 @@ void payload(void) val_set_status(pe_index, RESULT_PASS); } -uint32_t error013_entry(void) +uint32_t error013_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/error014.c b/test_pool/mpam/error014.c index 8e2f3773..3191aaeb 100644 --- a/test_pool/mpam/error014.c +++ b/test_pool/mpam/error014.c @@ -156,12 +156,14 @@ payload(void) return; } -uint32_t error014_entry(void) +uint32_t +error014_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/feat001.c b/test_pool/mpam/feat001.c index 0bb594f8..77fe4309 100644 --- a/test_pool/mpam/feat001.c +++ b/test_pool/mpam/feat001.c @@ -22,7 +22,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 25 -#define TEST_RULE "" +#define TEST_RULE "VFJMZ" #define TEST_DESC "Check PARTID Disable functionality " /* Test algorithm - @@ -225,7 +225,7 @@ payload(void) /* Step 6 */ counter[0] = end_count; - val_print(INFO, "\n PARTID_X Counter (Scenario 1)= 0x%lx", counter[0]); + val_print(DEBUG, "\n PARTID_X Counter (Scenario 1)= 0x%lx", counter[0]); /* Counter should be non-zero */ if (counter[0] == 0) { @@ -292,7 +292,7 @@ payload(void) val_mpam_csumon_disable(msc_index); counter[1] = end_count; - val_print(INFO, "\n PARTID_X Counter (Scenario 2)= 0x%lx", counter[1]); + val_print(DEBUG, "\n PARTID_X Counter (Scenario 2)= 0x%lx", counter[1]); /* Step 10: Validate Value B < Value A */ /* Txn tagged with PARTID_Y but monitor counts PARTID X. PARTID_X is disabled, so @@ -355,7 +355,7 @@ payload(void) val_mpam_csumon_disable(msc_index); counter[2] = end_count; - val_print(INFO, "\n PARTID_X Counter (Scenario 3)= 0x%lx", counter[2]); + val_print(DEBUG, "\n PARTID_X Counter (Scenario 3)= 0x%lx", counter[2]); /* With PARTID_Y disabled and PARTID_X enabled, CPOR settings of PARTID_X must be restored by the H/W. PARTID_Y cache lines should be evicted by txn tagged with @@ -391,11 +391,14 @@ payload(void) return; } -uint32_t feat001_entry(void) +uint32_t feat001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + /* Legacy MPAM execution runs this test on one PE. */ + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/intr001.c b/test_pool/mpam/intr001.c index 4884870d..39efbfeb 100644 --- a/test_pool/mpam/intr001.c +++ b/test_pool/mpam/intr001.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 12 #define TEST_DESC "Check Level-Sensitive Error Interrupt " -#define TEST_RULE "" +#define TEST_RULE "GLPPK" static uint32_t msc_index; static uint32_t intr_num; @@ -158,12 +158,14 @@ void payload(void) return; } -uint32_t intr001_entry(void) +uint32_t intr001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/intr002.c b/test_pool/mpam/intr002.c index 9ae86900..a4ced860 100644 --- a/test_pool/mpam/intr002.c +++ b/test_pool/mpam/intr002.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 13 #define TEST_DESC "Check MSC Edge-Trigger Error Interrupt" -#define TEST_RULE "" +#define TEST_RULE "KVGWS" static uint32_t msc_index; static uint32_t intr_num; @@ -155,12 +155,14 @@ void payload(void) return; } -uint32_t intr002_entry(void) +uint32_t intr002_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/intr003.c b/test_pool/mpam/intr003.c index 44b17689..4417bde5 100644 --- a/test_pool/mpam/intr003.c +++ b/test_pool/mpam/intr003.c @@ -23,7 +23,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 14 #define TEST_DESC "Check MBWU Mon Overflow interrupt " -#define TEST_RULE "" +#define TEST_RULE "YLCVK" static uint32_t msc_index; static uint32_t intr_num; @@ -100,7 +100,7 @@ void payload(void) if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) != MPAM_RSRC_TYPE_MEMORY) { - val_print(INFO, "\n MSC %d not a memory node. Skipping MSC", + val_print(DEBUG, "\n MSC %d not a memory node. Skipping MSC", msc_index); continue; } @@ -225,12 +225,14 @@ void payload(void) return; } -uint32_t intr003_entry(void) +uint32_t intr003_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/intr004.c b/test_pool/mpam/intr004.c index 4117985c..e2fdcda3 100644 --- a/test_pool/mpam/intr004.c +++ b/test_pool/mpam/intr004.c @@ -317,11 +317,14 @@ void payload(void) val_set_status(pe_index, RESULT_PASS); } -uint32_t intr004_entry(void) +uint32_t +intr004_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/intr005.c b/test_pool/mpam/intr005.c index 860ef616..be3ae4af 100644 --- a/test_pool/mpam/intr005.c +++ b/test_pool/mpam/intr005.c @@ -25,7 +25,7 @@ #define TEST_NUM ACS_MPAM_ERROR_TEST_NUM_BASE + 19 #define TEST_DESC "Check MBWU Oflow MSI interrupt status " -#define TEST_RULE "" +#define TEST_RULE "YJCDR" #define TEST_BUF_SIZE SIZE_1M @@ -214,6 +214,11 @@ void payload(void) continue; } + if (val_gic_its_configure() != ACS_STATUS_PASS) { + val_print(DEBUG, "\n ITS initialization failed; skipping MSI test"); + goto cleanup; + } + test_skip = 0; status = val_mpam_msc_request_msi(msc_index, device_id, its_id, @@ -332,11 +337,13 @@ void payload(void) val_set_status(pe_index, RESULT_PASS); } -uint32_t intr005_entry(void) +uint32_t intr005_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/intr006.c b/test_pool/mpam/intr006.c index 2f5c5db1..0bb21c58 100644 --- a/test_pool/mpam/intr006.c +++ b/test_pool/mpam/intr006.c @@ -151,6 +151,11 @@ void payload(void) break; } + if (val_gic_its_configure() != ACS_STATUS_PASS) { + val_print(DEBUG, "\n ITS initialization failed; skipping MSI test"); + break; + } + /* Install the ISR once per MSC loop, then route the interrupt. */ if (!handler_installed) { status = val_gic_install_isr(msi_intr_num, intr_handler); @@ -259,12 +264,13 @@ void payload(void) val_set_status(pe_index, RESULT_PASS); } -uint32_t intr006_entry(void) +uint32_t intr006_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; /* Standard ACS test entry/exit flow. */ + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/mem001.c b/test_pool/mpam/mem001.c index a43cca8d..ef9cd701 100644 --- a/test_pool/mpam/mem001.c +++ b/test_pool/mpam/mem001.c @@ -27,6 +27,7 @@ #define TEST_RULE "" #define MBWPBM_SCENARIO_MAX 10 +#define MPAM_TEST_MAX_RSRC 10 static uint64_t mpam2_el2_temp; typedef struct { @@ -84,7 +85,6 @@ static void payload(void) { - uint8_t enabled_scenarios = 0; uint16_t minmax_partid; uint16_t index; uint32_t msc_index; @@ -101,7 +101,7 @@ void payload(void) uint64_t mpam2_el2 = 0; uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t total_nodes = val_mpam_get_msc_count(); - uint64_t counter[MBWPBM_SCENARIO_MAX][total_nodes][10]; + uint64_t counter[MBWPBM_SCENARIO_MAX][total_nodes][MPAM_TEST_MAX_RSRC]; minmax_partid = DEFAULT_PARTID_MAX; @@ -113,6 +113,12 @@ void payload(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + if (rsrc_node_cnt > MPAM_TEST_MAX_RSRC) { + val_print(ERROR, "\n Resource count %d exceeds test limit", rsrc_node_cnt); + val_set_status(pe_index, RESULT_FAIL(04)); + return; + } + val_print(DEBUG, "\n msc index = %d", msc_index); val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); @@ -135,7 +141,7 @@ void payload(void) minmax_partid = GET_MIN_VALUE(minmax_partid, val_mpam_get_max_partid(msc_index)); } - val_print(INFO, + val_print(DEBUG, "\n %d MSC Memory Nodes support MBW Portion Partitioning", mbwpbm_node_cnt); /* Skip this test if no MBWPBM supported MSC present in the system */ @@ -237,6 +243,7 @@ void payload(void) buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { val_set_status(pe_index, RESULT_SKIP(02)); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -257,16 +264,24 @@ void payload(void) val_print(ERROR, "\n Memory allocation of buffers failed"); val_set_status(pe_index, RESULT_FAIL(02)); + if (dest_buf != NULL) + val_mem_free_at_address((uint64_t)dest_buf, buf_size); + if (src_buf != NULL) + val_mem_free_at_address((uint64_t)src_buf, buf_size); + /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(INFO, + val_print(DEBUG, "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(03)); - return; + val_set_status(pe_index, RESULT_SKIP(03)); + val_mem_free_at_address((uint64_t)dest_buf, buf_size); + val_mem_free_at_address((uint64_t)src_buf, buf_size); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + return; } val_print(DEBUG, @@ -285,7 +300,7 @@ void payload(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n Start count is %llx", start_count); + val_print(DEBUG, "\n Start count is %llx", start_count); /* perform memory operation */ val_memcpy(src_buf, dest_buf, buf_size); @@ -297,17 +312,17 @@ void payload(void) }; end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n End count is %llx", end_count); + val_print(DEBUG, "\n End count is %llx", end_count); /* read the memory bandwidth usage monitor */ - counter[enabled_scenarios++][msc_index][rsrc_index] = + counter[index][msc_index][rsrc_index] = end_count - start_count; /* disable and reset the MBWU monitor */ val_mpam_memory_mbwumon_disable(msc_index); val_mpam_memory_mbwumon_reset(msc_index); - val_print(INFO, + val_print(DEBUG, "\n byte_count = 0x%llx bytes", end_count - start_count); /* Free the buffers to the heap manager */ @@ -321,7 +336,8 @@ void payload(void) val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); /* Compare the stream copy latencies for all the scenarios */ - for (index = 1; index < enabled_scenarios; index++) { + for (index = 1; + index < sizeof(mbwpbm_config_data) / sizeof(mbwpbm_config_data[0]); index++) { for (msc_index = 0; msc_index < total_nodes; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); @@ -349,12 +365,13 @@ void payload(void) return; } -uint32_t mem001_entry(void) +uint32_t mem001_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/mem002.c b/test_pool/mpam/mem002.c index a2abed27..8d0e1ab6 100644 --- a/test_pool/mpam/mem002.c +++ b/test_pool/mpam/mem002.c @@ -31,6 +31,7 @@ #define BW2_PERCENTAGE 10 // Min BW limit partitioning scenario 2 #define NUM_PE_CONT 04 // Number of PEs used to create BW contention #define MBWMIN_SCENARIO_MAX 2 +#define MPAM_TEST_MAX_RSRC 10 static uint8_t contend_flag; static uint32_t num_pe_cont; @@ -222,7 +223,7 @@ payload_primary(void) uint32_t scenario_cnt = 0; uint32_t num_pe = val_pe_get_num(); uint32_t total_nodes = val_mpam_get_msc_count(); - uint64_t counter[total_nodes][10][MBWMIN_SCENARIO_MAX]; + uint64_t counter[total_nodes][MPAM_TEST_MAX_RSRC][MBWMIN_SCENARIO_MAX]; minmax_partid = DEFAULT_PARTID_MAX; primary_pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); @@ -235,6 +236,12 @@ payload_primary(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + if (rsrc_node_cnt > MPAM_TEST_MAX_RSRC) { + val_print(ERROR, "\n Resource count %d exceeds test limit", rsrc_node_cnt); + val_set_status(primary_pe_index, RESULT_FAIL(06)); + return; + } + val_print(DEBUG, "\n msc index = %d", msc_index); val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); @@ -259,7 +266,7 @@ payload_primary(void) /* Skip this test if no MIN BW supported MPAM memory node present in the system */ if (mbwmin_node_cnt == 0) { - val_print(INFO, + val_print(DEBUG, "\n %d MSC Memory Nodes support MBW Min Limit Partitioning", mbwmin_node_cnt); val_set_status(primary_pe_index, RESULT_SKIP(01)); return; @@ -300,6 +307,14 @@ payload_primary(void) if (val_mpam_msc_supports_ris(msc_index)) val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); + if (!val_mpam_get_mbwumon_count(msc_index)) { + val_print(DEBUG, + "\n No MBWU Monitor found to validate the test. Skipping test"); + val_set_status(primary_pe_index, RESULT_SKIP(02)); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2); + return; + } + /* Disable MBWPBM partitioning for the current memory msc_index */ if (val_mpam_msc_supports_mbwpbm(msc_index)) val_mpam_configure_mbwpbm(msc_index, minmax_partid, 100); @@ -349,14 +364,6 @@ payload_primary(void) } } - if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(INFO, - "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(02)); - contend_flag = 0; - return; - } - val_print(DEBUG, "\n Using MBWU monitor to measure MBW during buffer copy"); /* configure MBWU Monitor for this memory resource node */ @@ -372,18 +379,18 @@ payload_primary(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n Start Count = 0x%llx", start_count); + val_print(DEBUG, "\n Start Count = 0x%llx", start_count); /* perform memory operation */ val_memcpy((void *)src_buf, (void *)dest_buf, buf_size); /* Wait for some time before the memcpy settles and counters update */ val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n End Count = 0x%llx", end_count); + val_print(DEBUG, "\n End Count = 0x%llx", end_count); /* read the memory bandwidth usage monitor */ counter[msc_index][rsrc_index][scenario_cnt] = end_count - start_count; - val_print(INFO, + val_print(DEBUG, "\n Byte count = 0x%llx", end_count - start_count); /* disable and reset the MBWU monitor */ @@ -428,19 +435,19 @@ payload_primary(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n Start Count = 0x%llx", start_count); + val_print(DEBUG, "\n Start Count = 0x%llx", start_count); /* perform memory operation */ val_memcpy((void *)src_buf, (void *)dest_buf, buf_size); /* Wait for some time before the memcpy settles and counters update */ val_time_delay_ms(TIMEOUT_MEDIUM); end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n End Count = 0x%llx", end_count); + val_print(DEBUG, "\n End Count = 0x%llx", end_count); /* read the memory bandwidth usage monitor */ counter[msc_index][rsrc_index][scenario_cnt] = end_count - start_count; - val_print(INFO, + val_print(DEBUG, "\n Byte Count = 0x%llx", end_count - start_count); /* disable and reset the MBWU monitor */ @@ -456,7 +463,7 @@ payload_primary(void) } /* Free the copy buffers to the heap manager */ - val_mem_free_shared_memcpybuf(NUM_PE_CONT); + val_mem_free_shared_memcpybuf(num_pe_cont); } } } @@ -502,12 +509,13 @@ payload_primary(void) } uint32_t -mem002_entry(void) +mem002_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/mem003.c b/test_pool/mpam/mem003.c index c638aae8..68f1ce5b 100644 --- a/test_pool/mpam/mem003.c +++ b/test_pool/mpam/mem003.c @@ -27,6 +27,7 @@ #define TEST_RULE "" #define MBWMAX_SCENARIO_MAX 10 +#define MPAM_TEST_MAX_RSRC 10 static uint64_t mpam2_el2_temp; typedef struct { @@ -83,7 +84,6 @@ static void payload(void) { - uint8_t enabled_scenarios = 0; uint16_t minmax_partid; uint16_t index; uint32_t msc_index; @@ -100,7 +100,7 @@ void payload(void) uint64_t mpam2_el2 = 0; uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid());; uint32_t total_nodes = val_mpam_get_msc_count(); - uint64_t counter[MBWMAX_SCENARIO_MAX][total_nodes][10]; + uint64_t counter[MBWMAX_SCENARIO_MAX][total_nodes][MPAM_TEST_MAX_RSRC]; minmax_partid = DEFAULT_PARTID_MAX; @@ -112,6 +112,12 @@ void payload(void) rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + if (rsrc_node_cnt > MPAM_TEST_MAX_RSRC) { + val_print(ERROR, "\n Resource count %d exceeds test limit", rsrc_node_cnt); + val_set_status(pe_index, RESULT_FAIL(04)); + return; + } + val_print(DEBUG, "\n msc index = %d", msc_index); val_print(DEBUG, "\n Resource count = %d ", rsrc_node_cnt); @@ -134,7 +140,7 @@ void payload(void) minmax_partid = GET_MIN_VALUE(minmax_partid, val_mpam_get_max_partid(msc_index)); } - val_print(INFO, + val_print(DEBUG, "\n %d MSC Memory Nodes support MBW Max Limit Partitioning", mbwmax_node_cnt); /* Skip this test if no MBWMAX supported MSC present in the system */ @@ -236,6 +242,7 @@ void payload(void) buf_size = get_buffer_size(msc_index, rsrc_index, addr_len, index); if (buf_size == ACS_STATUS_SKIP) { val_set_status(pe_index, RESULT_SKIP(02)); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } @@ -256,16 +263,24 @@ void payload(void) val_print(ERROR, "\n Memory allocation of buffers failed"); val_set_status(pe_index, RESULT_FAIL(02)); + if (dest_buf != NULL) + val_mem_free_at_address((uint64_t)dest_buf, buf_size); + if (src_buf != NULL) + val_mem_free_at_address((uint64_t)src_buf, buf_size); + /* Restore MPAM2_EL2 settings */ val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); return; } if (!val_mpam_get_mbwumon_count(msc_index)) { - val_print(INFO, + val_print(DEBUG, "\n No MBWU Monitor found to validate the test. Skipping test"); - val_set_status(pe_index, RESULT_SKIP(03)); - return; + val_set_status(pe_index, RESULT_SKIP(03)); + val_mem_free_at_address((uint64_t)dest_buf, buf_size); + val_mem_free_at_address((uint64_t)src_buf, buf_size); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + return; } val_print(DEBUG, @@ -284,7 +299,7 @@ void payload(void) }; start_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n Start count is %llx", start_count); + val_print(DEBUG, "\n Start count is %llx", start_count); /* perform memory operation */ val_memcpy(src_buf, dest_buf, buf_size); @@ -296,17 +311,17 @@ void payload(void) }; end_count = val_mpam_memory_mbwumon_read_count(msc_index); - val_print(INFO, "\n End count is %llx", end_count); + val_print(DEBUG, "\n End count is %llx", end_count); /* read the memory bandwidth usage monitor */ - counter[enabled_scenarios++][msc_index][rsrc_index] = + counter[index][msc_index][rsrc_index] = end_count - start_count; /* disable and reset the MBWU monitor */ val_mpam_memory_mbwumon_disable(msc_index); val_mpam_memory_mbwumon_reset(msc_index); - val_print(INFO, + val_print(DEBUG, "\n byte_count = 0x%llx bytes", end_count - start_count); /* Free the buffers to the heap manager */ @@ -320,7 +335,8 @@ void payload(void) val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); /* Compare the stream copy latencies for all the scenarios */ - for (index = 1; index < enabled_scenarios; index++) { + for (index = 1; + index < sizeof(mbwmax_config_data) / sizeof(mbwmax_config_data[0]); index++) { for (msc_index = 0; msc_index < total_nodes; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); @@ -350,12 +366,13 @@ void payload(void) uint32_t -mem003_entry(void) +mem003_entry(uint32_t num_pe) { - uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/monitor001.c b/test_pool/mpam/monitor001.c index f737be93..86d8f7ac 100644 --- a/test_pool/mpam/monitor001.c +++ b/test_pool/mpam/monitor001.c @@ -297,11 +297,14 @@ static void payload(void) return; } -uint32_t monitor001_entry(void) +uint32_t +monitor001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/monitor002.c b/test_pool/mpam/monitor002.c index 3ce84c5f..7f5265d3 100644 --- a/test_pool/mpam/monitor002.c +++ b/test_pool/mpam/monitor002.c @@ -305,11 +305,12 @@ static void payload(void) return; } -uint32_t monitor002_entry(void) +uint32_t monitor002_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/monitor003.c b/test_pool/mpam/monitor003.c index 23cd5b9e..390b10c2 100644 --- a/test_pool/mpam/monitor003.c +++ b/test_pool/mpam/monitor003.c @@ -292,11 +292,12 @@ static void payload(void) return; } -uint32_t monitor003_entry(void) +uint32_t monitor003_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/monitor004.c b/test_pool/mpam/monitor004.c index a9df6e7e..5af072b4 100644 --- a/test_pool/mpam/monitor004.c +++ b/test_pool/mpam/monitor004.c @@ -292,11 +292,12 @@ static void payload(void) return; } -uint32_t monitor004_entry(void) +uint32_t monitor004_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/monitor005.c b/test_pool/mpam/monitor005.c index 3d02b866..5730b021 100644 --- a/test_pool/mpam/monitor005.c +++ b/test_pool/mpam/monitor005.c @@ -81,7 +81,7 @@ payload(void) GET_MIN_VALUE(test_partid, max_partid - 1); } - val_print(INFO, "\n Selected PARTID = %d", test_partid); + val_print(DEBUG, "\n Selected PARTID = %d", test_partid); /* Iterate through all available LLC MSCs and their resources */ for (msc_index = 0; msc_index < msc_cnt; msc_index++) { @@ -235,11 +235,14 @@ payload(void) return; } -uint32_t monitor005_entry(void) +uint32_t +monitor005_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/monitor006.c b/test_pool/mpam/monitor006.c index 423d5bbe..778d4da3 100644 --- a/test_pool/mpam/monitor006.c +++ b/test_pool/mpam/monitor006.c @@ -192,11 +192,14 @@ payload(void) return; } -uint32_t monitor006_entry(void) +uint32_t +monitor006_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/monitor007.c b/test_pool/mpam/monitor007.c index 5e5b6280..2c709f40 100644 --- a/test_pool/mpam/monitor007.c +++ b/test_pool/mpam/monitor007.c @@ -23,7 +23,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_MEMORY_TEST_NUM_BASE + 5 -#define TEST_RULE "" +#define TEST_RULE "XSTRM" #define TEST_DESC "Check MBWU OFLOW_FRZ overflow behavior" #define TEST_BUF_SIZE SIZE_1M @@ -278,11 +278,13 @@ payload(void) return; } -uint32_t monitor007_entry(void) +uint32_t monitor007_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/monitor008.c b/test_pool/mpam/monitor008.c index 43292e16..e15bc286 100644 --- a/test_pool/mpam/monitor008.c +++ b/test_pool/mpam/monitor008.c @@ -36,7 +36,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_MEMORY_TEST_NUM_BASE + 6 -#define TEST_RULE "" +#define TEST_RULE "GNQFY" #define TEST_DESC "Check MBWU MSMON OFLOW Reset behavior " #define TEST_BUF_SIZE SIZE_1M @@ -285,11 +285,13 @@ payload(void) return; } -uint32_t monitor008_entry(void) +uint32_t monitor008_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/mpam006.c b/test_pool/mpam/mpam006.c index 667e67cc..7f29b1ef 100644 --- a/test_pool/mpam/mpam006.c +++ b/test_pool/mpam/mpam006.c @@ -43,7 +43,7 @@ program_all_monitors_with_pmg(uint16_t partid, uint8_t pmg) uint32_t csumon_count = 0; uint32_t rsrc_node_cnt, rsrc_index; - val_print(INFO, "\n Programming all MSCs to filter PMG value %d", pmg); + val_print(DEBUG, "\n Programming all MSCs to filter PMG value %d", pmg); for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); @@ -78,7 +78,7 @@ program_all_monitors_with_pmg(uint16_t partid, uint8_t pmg) /* Skip if the MSC's resource does not implement CSUMON or has max_pmg < programmable PMG */ if (csumon_count == 0 || max_pmg < pmg) { - val_print(INFO, "\n Skipping MSC resource %d", rsrc_index); + val_print(DEBUG, "\n Skipping MSC resource %d", rsrc_index); continue; } @@ -190,8 +190,8 @@ read_all_msc_csu_counters(uint32_t expected_count) } storage_count = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n msc index = %d", msc_index); - val_print(INFO, " storage count = %d", storage_count); + val_print(DEBUG, "\n msc index = %d", msc_index); + val_print(DEBUG, " storage count = %d", storage_count); /* Expected count || Storage count -> Status */ /* 0 || 0 -> 1 */ @@ -278,7 +278,7 @@ payload(void) mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PMG_D_SHIFT+7, MPAMn_ELx_PMG_D_SHIFT); - val_print(INFO, "\n Programming mpam2_el2 with PMG=0 %d", pmg0); + val_print(DEBUG, "\n Programming mpam2_el2 with PMG=0 %d", pmg0); mpam2_el2 |= (((uint64_t)pmg0 << MPAMn_ELx_PMG_D_SHIFT) | ((uint64_t)partid << MPAMn_ELx_PARTID_D_SHIFT)); @@ -314,7 +314,7 @@ payload(void) mpam2_el2 |= (((uint64_t)pmg1 << MPAMn_ELx_PMG_D_SHIFT) | ((uint64_t)partid << MPAMn_ELx_PARTID_D_SHIFT)); - val_print(INFO, "\n Programming mpam2_el2 with PMG=1 %d", pmg1); + val_print(DEBUG, "\n Programming mpam2_el2 with PMG=1 %d", pmg1); val_mpam_reg_write(MPAM2_EL2, mpam2_el2); diff --git a/test_pool/mpam/partition001.c b/test_pool/mpam/partition001.c index c1770ef7..ad767c29 100644 --- a/test_pool/mpam/partition001.c +++ b/test_pool/mpam/partition001.c @@ -24,7 +24,7 @@ #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 1 -#define TEST_RULE "" +#define TEST_RULE "XPPGG" #define TEST_DESC "Check CPOR Partitioning " #define CPOR_SCENARIO_MAX 10 @@ -275,11 +275,13 @@ static void payload(void) return; } -uint32_t partition001_entry(void) +uint32_t partition001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/partition002.c b/test_pool/mpam/partition002.c index 530d5c8b..bde1abc6 100644 --- a/test_pool/mpam/partition002.c +++ b/test_pool/mpam/partition002.c @@ -24,7 +24,7 @@ #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 2 -#define TEST_RULE "" +#define TEST_RULE "ZHBXH" #define TEST_DESC "Check CCAP Partitioning " #define CCAP_SCENARIO_MAX 10 @@ -276,11 +276,13 @@ static void payload(void) return; } -uint32_t partition002_entry(void) +uint32_t partition002_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/partition003.c b/test_pool/mpam/partition003.c index 8bd5ce87..3eef0fad 100644 --- a/test_pool/mpam/partition003.c +++ b/test_pool/mpam/partition003.c @@ -281,11 +281,12 @@ static void payload(void) return; } -uint32_t partition003_entry(void) +uint32_t partition003_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* This check is when user is forcing us to skip this test */ diff --git a/test_pool/mpam/partition004.c b/test_pool/mpam/partition004.c index 8397d7ca..4a20444d 100644 --- a/test_pool/mpam/partition004.c +++ b/test_pool/mpam/partition004.c @@ -22,7 +22,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 4 -#define TEST_RULE "" +#define TEST_RULE "BDRCM" #define TEST_DESC "Check CASSOC Partitioning " /* Test algorithm - @@ -80,8 +80,8 @@ payload(void) /* Check if LLC is valid */ if (llc_idx == CACHE_TABLE_EMPTY) { val_print(DEBUG, "\n No LLC found, skipping test"); - return; val_set_status(index, RESULT_SKIP(1)); + return; } /* Get the LLC Cache ID */ @@ -105,8 +105,13 @@ payload(void) GET_MIN_VALUE(test_partid, max_partid - 1); } - val_print(INFO, "\n Selected PARTID = %d", test_partid); + val_print(DEBUG, "\n Selected PARTID = %d", test_partid); + if (test_partid < 2) { + val_print(DEBUG, "\n Three consecutive test PARTIDs are required, skipping test"); + val_set_status(index, RESULT_SKIP(3)); + return; + } /* Iterate through all available LLC MSCs and their resources */ for (msc_index = 0; msc_index < msc_cnt; msc_index++) { @@ -126,7 +131,7 @@ payload(void) in unexpected behavior in the test */ if (val_cache_get_associativity(cache_identifier) < 4) { - val_print(INFO, + val_print(DEBUG, "\n LLC is less than 4-way, skipping MSC"); continue; } @@ -207,13 +212,17 @@ payload(void) status = val_mpam_program_el2(test_partid, DEFAULT_PMG); if (status) { val_print(ERROR, "\n MPAM2_EL2 programming failed"); + val_mpam_csumon_disable(msc_index); + val_mpam_reg_write(MPAM2_EL2, saved_el2); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); val_mem_issue_dsb(); - val_memory_free_aligned(src_buf); - val_memory_free_aligned(dest_buf); + if (dest_buf != NULL) + val_memory_free_pages(dest_buf, num_pages); + if (src_buf != NULL) + val_memory_free_pages(src_buf, num_pages); val_set_status(index, RESULT_FAIL(02)); return; } @@ -268,13 +277,17 @@ payload(void) status = val_mpam_program_el2(test_partid - 1, DEFAULT_PMG); if (status) { val_print(ERROR, "\n MPAM2_EL2 programming failed"); + val_mpam_csumon_disable(msc_index); + val_mpam_reg_write(MPAM2_EL2, saved_el2); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); val_mem_issue_dsb(); - val_memory_free_aligned(src_buf); - val_memory_free_aligned(dest_buf); + if (dest_buf != NULL) + val_memory_free_pages(dest_buf, num_pages); + if (src_buf != NULL) + val_memory_free_pages(src_buf, num_pages); val_set_status(index, RESULT_FAIL(03)); return; } @@ -329,13 +342,17 @@ payload(void) status = val_mpam_program_el2(test_partid - 2, DEFAULT_PMG); if (status) { val_print(ERROR, "\n MPAM2_EL2 programming failed"); + val_mpam_csumon_disable(msc_index); + val_mpam_reg_write(MPAM2_EL2, saved_el2); /* Free the buffers to the heap manager */ val_pe_cache_invalidate_range((uint64_t)src_buf, BUFFER_SIZE); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); val_mem_issue_dsb(); - val_memory_free_aligned(src_buf); - val_memory_free_aligned(dest_buf); + if (dest_buf != NULL) + val_memory_free_pages(dest_buf, num_pages); + if (src_buf != NULL) + val_memory_free_pages(src_buf, num_pages); val_set_status(index, RESULT_FAIL(04)); return; } @@ -397,11 +414,13 @@ payload(void) return; } -uint32_t partition004_entry(void) +uint32_t partition004_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/partition005.c b/test_pool/mpam/partition005.c index deb11c0c..9ba4b7d1 100644 --- a/test_pool/mpam/partition005.c +++ b/test_pool/mpam/partition005.c @@ -23,7 +23,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 5 -#define TEST_RULE "" +#define TEST_RULE "VZBFH" #define TEST_DESC "Check CMAX Partitioning with softlimit" /* Test algorithm @@ -185,7 +185,7 @@ payload(void) /* Save the current MPAM2_EL2 settings */ saved_el2 = val_mpam_reg_read(MPAM2_EL2); - val_print(INFO, "\n Scenario 1: PARTID_X without SOFTLIM"); + val_print(DEBUG, "\n Scenario 1: PARTID_X without SOFTLIM"); /* Step 4: Program MPAM2_EL2 with partid_x and default PMG */ status = val_mpam_program_el2(partid_x, DEFAULT_PMG); @@ -210,7 +210,7 @@ payload(void) /* Step 6 - Read the Cache line count used by PARTID X from CSU MON */ counter[0] = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n Scenario 1: End Count = 0x%lx", counter[0]); + val_print(DEBUG, "\n Scenario 1: End Count = 0x%lx", counter[0]); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -282,7 +282,7 @@ payload(void) /* Step 11: Measure cache usage again with the CSU monitor */ counter[1] = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n Scenario 2: End Count = 0x%lx", counter[1]); + val_print(DEBUG, "\n Scenario 2: End Count = 0x%lx", counter[1]); /* Compare the result. Counter[1] should be more than Counter[0]. The softlimiting should allow some of the disabled PARTID_Y's cache lines to be used by PARTID_X */ @@ -352,11 +352,13 @@ payload(void) return; } -uint32_t partition005_entry(void) +uint32_t partition005_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/partition006.c b/test_pool/mpam/partition006.c index b25aa17a..f6882116 100644 --- a/test_pool/mpam/partition006.c +++ b/test_pool/mpam/partition006.c @@ -23,7 +23,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_CACHE_TEST_NUM_BASE + 6 -#define TEST_RULE "" +#define TEST_RULE "CXZDR" #define TEST_DESC "Check CMIN resource controls " /* Test Algorithm @@ -199,7 +199,7 @@ payload(void) /* Read the monitor counter for PARTID_X */ counter[0] = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n PARTID_X Counter: 0x%x", counter[0]); + val_print(DEBUG, "\n PARTID_X Counter: 0x%x", counter[0]); /* Disable CSU MON */ val_mpam_csumon_disable(msc_index); @@ -237,7 +237,7 @@ payload(void) /* Read the monitor counter for PARTID_Y */ counter[1] = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n PARTID_Y Counter: 0x%x", counter[1]); + val_print(DEBUG, "\n PARTID_Y Counter: 0x%x", counter[1]); /* Read PARTID_X counter after the second buffer copy */ val_mpam_configure_csu_mon(msc_index, partid_x, DEFAULT_PMG, 0); @@ -248,7 +248,7 @@ payload(void) } counter[0] = val_mpam_read_csumon(msc_index); - val_print(INFO, + val_print(DEBUG, "\n PARTID_X Counter after PARTID_Y workload: 0x%x", counter[0]); val_pe_cache_invalidate_range((uint64_t)dest_buf, BUFFER_SIZE); @@ -271,7 +271,7 @@ payload(void) val_mpam_configure_csu_mon(msc_index, partid_z, DEFAULT_PMG, 0); counter[2] = val_mpam_read_csumon(msc_index); - val_print(INFO, + val_print(DEBUG, "\n PARTID_Z Counter before workload: 0x%x", counter[2]); /* Step 8: Perform a memory workload for PARTID_Z */ @@ -295,7 +295,7 @@ payload(void) } counter[2] = val_mpam_read_csumon(msc_index); - val_print(INFO, "\n PARTID_Z Counter after workload: %x", counter[2]); + val_print(DEBUG, "\n PARTID_Z Counter after workload: %x", counter[2]); /* Read PARTID_X and PARTID_Y counters after PARTID_Z workload */ val_mpam_configure_csu_mon(msc_index, partid_x, DEFAULT_PMG, 0); @@ -306,7 +306,7 @@ payload(void) } counter[0] = val_mpam_read_csumon(msc_index); - val_print(INFO, + val_print(DEBUG, "\n PARTID_X Counter after PARTID_Z workload: 0x%x", counter[0]); val_mpam_configure_csu_mon(msc_index, partid_y, DEFAULT_PMG, 0); @@ -317,7 +317,7 @@ payload(void) } counter[1] = val_mpam_read_csumon(msc_index); - val_print(INFO, + val_print(DEBUG, "\n PARTID_Y Counter after PARTID_Z workload: 0x%x", counter[1]); if (counter[1] > counter[0]) { @@ -393,11 +393,13 @@ payload(void) return; } -uint32_t partition006_entry(void) +uint32_t partition006_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); /* Check if test needs to be skipped - based on user configuration */ diff --git a/test_pool/mpam/reg001.c b/test_pool/mpam/reg001.c index f5c2ab14..f0841c2e 100644 --- a/test_pool/mpam/reg001.c +++ b/test_pool/mpam/reg001.c @@ -23,7 +23,7 @@ #include "val_interface.h" #define TEST_NUM ACS_MPAM_REGISTER_TEST_NUM_BASE + 1 -#define TEST_RULE "" +#define TEST_RULE "CFXGZ" #define TEST_DESC "Check MPAM Version EXT Bit Check " static void payload(void) @@ -77,12 +77,14 @@ static void payload(void) return; } -uint32_t reg001_entry(void) +uint32_t reg001_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/reg002.c b/test_pool/mpam/reg002.c index e6eb4583..7e9e81d4 100644 --- a/test_pool/mpam/reg002.c +++ b/test_pool/mpam/reg002.c @@ -59,12 +59,13 @@ static void payload(void) return; } -uint32_t reg002_entry(void) +uint32_t reg002_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/reg003.c b/test_pool/mpam/reg003.c index 9437f8ff..270bd737 100644 --- a/test_pool/mpam/reg003.c +++ b/test_pool/mpam/reg003.c @@ -249,12 +249,13 @@ static void payload(void) return; } -uint32_t reg003_entry(void) +uint32_t reg003_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) diff --git a/test_pool/mpam/reg004.c b/test_pool/mpam/reg004.c index bfbd967b..28842a49 100644 --- a/test_pool/mpam/reg004.c +++ b/test_pool/mpam/reg004.c @@ -22,7 +22,7 @@ #include "val_interface.h" #define TEST_NUM (ACS_MPAM_REGISTER_TEST_NUM_BASE + 4) -#define TEST_RULE "" +#define TEST_RULE "FXVBB" #define TEST_DESC "Check MPAM for RME Feature Test " static void payload(void) @@ -87,12 +87,14 @@ static void payload(void) } -uint32_t reg004_entry(void) +uint32_t reg004_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = val_pe_get_num(); + num_pe = val_pe_get_num(); + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) @@ -101,7 +103,7 @@ uint32_t reg004_entry(void) /* get the result from all PE and check for failure */ status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, ACS_END(TEST_NUM), NULL); + val_report_status(0, ACS_END(TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/mpam/reg005.c b/test_pool/mpam/reg005.c index 051b8c62..a3f35ac3 100644 --- a/test_pool/mpam/reg005.c +++ b/test_pool/mpam/reg005.c @@ -22,7 +22,7 @@ #include "val_interface.h" #define TEST_NUM (ACS_MPAM_REGISTER_TEST_NUM_BASE + 5) -#define TEST_RULE "" +#define TEST_RULE "GDMQZ" #define TEST_DESC "Check MSC Four-Space Region Test " static void payload(void) @@ -68,12 +68,14 @@ static void payload(void) return; } -uint32_t reg005_entry(void) +uint32_t reg005_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) @@ -82,7 +84,7 @@ uint32_t reg005_entry(void) /* get the result from all PE and check for failure */ status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, ACS_END(TEST_NUM), NULL); + val_report_status(0, ACS_END(TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/mpam/reg006.c b/test_pool/mpam/reg006.c index f3f7320c..bd304110 100644 --- a/test_pool/mpam/reg006.c +++ b/test_pool/mpam/reg006.c @@ -22,7 +22,7 @@ #include "val_interface.h" #define TEST_NUM (ACS_MPAM_REGISTER_TEST_NUM_BASE + 6) -#define TEST_RULE "" +#define TEST_RULE "RNSLZ" #define TEST_DESC "Check NFU bit when PARTID NRW is impl " static void payload(void) @@ -66,12 +66,14 @@ static void payload(void) return; } -uint32_t reg006_entry(void) +uint32_t reg006_entry(uint32_t num_pe) { uint32_t status = ACS_STATUS_FAIL; - uint32_t num_pe = 1; + num_pe = 1; + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); if (status != ACS_STATUS_SKIP) @@ -80,7 +82,7 @@ uint32_t reg006_entry(void) /* get the result from all PE and check for failure */ status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, ACS_END(TEST_NUM), NULL); + val_report_status(0, ACS_END(TEST_NUM), TEST_RULE); return status; } diff --git a/tools/scripts/generate_rule_checklist.py b/tools/scripts/generate_rule_checklist.py new file mode 100644 index 00000000..99cb8263 --- /dev/null +++ b/tools/scripts/generate_rule_checklist.py @@ -0,0 +1,403 @@ +## @file + # Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +"""Generate rule coverage checklist Markdown and CSV from JSON.""" + +from __future__ import annotations + +import argparse +import csv +import json +import os +import re +from collections import Counter +from pathlib import Path +from urllib.parse import quote + + +DEFAULT_STATUS_ORDER = [ + "COVERED", + "NOT_COVERED", +] + +BASE_CSV_FIELDNAMES = [ + "Specification Rule ID", + "Status", + "Tests", + "Notes", +] + + +REPO_ROOT = Path(__file__).resolve().parents[2] +CSV_FORMULA_PREFIXES = ("=", "+", "-", "@") +SAFE_JSON_LABEL_RE = re.compile(r"^[A-Za-z0-9][A-Za-z0-9_. -]*$") + + +def resolve_path(path: Path) -> Path: + candidate = path if path.is_absolute() else REPO_ROOT / path + return candidate.resolve() + + +def resolve_output_path(path: Path) -> Path: + resolved = resolve_path(path) + try: + resolved.relative_to(REPO_ROOT) + except ValueError as exc: + raise ValueError(f"Output path must be within the repository: {path}") from exc + return resolved + + +def display_path(path: Path) -> str: + try: + return str(path.resolve().relative_to(REPO_ROOT)) + except ValueError: + return str(path) + + +def load_json(path: Path) -> dict: + with path.open(encoding="utf-8") as json_file: + return json.load(json_file) + + +def status_order(data: dict) -> list[str]: + return data.get("metadata", {}).get("status_order", DEFAULT_STATUS_ORDER) + + +def validate_safe_json_label(field_name: str, value: object) -> None: + if not isinstance(value, str) or not SAFE_JSON_LABEL_RE.fullmatch(value): + raise ValueError(f"Unsafe {field_name}: {value!r}") + + +def escape_markdown_text(value: object) -> str: + text = "" if value is None else str(value) + return ( + text.replace("\\", "\\\\") + .replace("|", "\\|") + .replace("[", "\\[") + .replace("]", "\\]") + .replace("<", "<") + .replace(">", ">") + ) + + +def escape_markdown_code(value: object) -> str: + text = "" if value is None else str(value) + return text.replace("\\", "\\\\").replace("`", "\\`") + + +def markdown_link_target(target: Path, base: Path) -> str: + try: + relative = os.path.relpath(target, start=base.parent) + except ValueError: + relative = target.as_posix() + return quote(Path(relative).as_posix(), safe="/._-~") + + +def validate(data: dict) -> None: + statuses = set(data["status_definitions"]) + rule_ids = [] + platforms = data.get("metadata", {}).get("platforms", []) + + if not isinstance(platforms, list): + raise ValueError("metadata.platforms must be a list") + + if len(platforms) != len(set(platforms)): + raise ValueError("Duplicate platform entries found") + + for platform in platforms: + validate_safe_json_label("platform name", platform) + + for status in statuses: + validate_safe_json_label("status", status) + + for status in status_order(data): + validate_safe_json_label("status_order entry", status) + if status not in statuses: + raise ValueError(f"status_order entry is not defined: {status}") + + for rule in data["rules"]: + validate_safe_json_label("rule_id", rule["rule_id"]) + validate_safe_json_label("status", rule["status"]) + rule_ids.append(rule["rule_id"]) + if rule["status"] not in statuses: + raise ValueError(f"Unknown status for {rule['rule_id']}: {rule['status']}") + + for sub_rule in rule.get("sub_rules", []): + validate_safe_json_label("sub_rule_id", sub_rule["sub_rule_id"]) + validate_safe_json_label("status", sub_rule["status"]) + if sub_rule["status"] not in statuses: + raise ValueError( + f"Unknown status for {rule['rule_id']}/{sub_rule['sub_rule_id']}: " + f"{sub_rule['status']}" + ) + + if len(rule_ids) != len(set(rule_ids)): + raise ValueError("Duplicate rule_id entries found") + + +def has_sub_rules(data: dict) -> bool: + return any(rule.get("sub_rules") for rule in data["rules"]) + + +def platform_names(data: dict) -> list[str]: + return data.get("metadata", {}).get("platforms", []) + + +def csv_fieldnames(data: dict) -> list[str]: + fieldnames = BASE_CSV_FIELDNAMES.copy() + insert_at = 1 + if has_sub_rules(data): + fieldnames.insert(insert_at, "Sub Rule ID") + insert_at += 1 + + for platform in platform_names(data): + fieldnames.insert(insert_at, platform) + insert_at += 1 + + return fieldnames + + +def platform_columns(data: dict, entry: dict) -> dict: + if entry.get("status") != "COVERED": + return {platform: "" for platform in platform_names(data)} + + platforms = entry.get("platforms", []) + if isinstance(platforms, dict): + applicable = { + platform + for platform, value in platforms.items() + if str(value).lower() in {"yes", "true", "1"} + } + else: + applicable = set(platforms) + + return { + platform: "Yes" if platform in applicable else "No" + for platform in platform_names(data) + } + + +def sanitize_csv_cell(value: object) -> str: + text = "" if value is None else str(value) + stripped = text.lstrip() + if stripped != "-" and stripped.startswith(CSV_FORMULA_PREFIXES): + return "'" + text + return text + + +def sanitize_csv_row(row: dict) -> dict: + return {key: sanitize_csv_cell(value) for key, value in row.items()} + + +def summary_entries(data: dict) -> list[dict]: + entries = [] + for rule in data["rules"]: + sub_rules = rule.get("sub_rules", []) + if sub_rules: + entries.extend(sub_rules) + else: + entries.append(rule) + return entries + + +def rule_rows(data: dict) -> list[dict]: + rows = [] + for rule in data["rules"]: + sub_rules = rule.get("sub_rules", []) + if sub_rules: + for sub_rule in sub_rules: + rows.append( + { + "Specification Rule ID": sanitize_csv_cell(rule["rule_id"]), + "Sub Rule ID": sanitize_csv_cell(sub_rule["sub_rule_id"]), + "Status": sanitize_csv_cell(sub_rule["status"]), + **sanitize_csv_row(platform_columns(data, sub_rule)), + "Tests": sanitize_csv_cell( + ", ".join(sub_rule.get("tests", [])) or "-" + ), + "Notes": sanitize_csv_cell(sub_rule.get("notes", "")), + } + ) + else: + rows.append( + { + "Specification Rule ID": sanitize_csv_cell(rule["rule_id"]), + "Sub Rule ID": "-", + "Status": sanitize_csv_cell(rule["status"]), + **sanitize_csv_row(platform_columns(data, rule)), + "Tests": sanitize_csv_cell( + ", ".join(rule.get("tests", [])) or "-" + ), + "Notes": sanitize_csv_cell(rule.get("notes", "")), + } + ) + return rows + + +def write_csv(data: dict, path: Path) -> None: + rows = rule_rows(data) + with path.open("w", encoding="utf-8", newline="") as csv_file: + writer = csv.DictWriter(csv_file, fieldnames=csv_fieldnames(data), extrasaction="ignore") + writer.writeheader() + writer.writerows(sanitize_csv_row(row) for row in rows) + + +def write_markdown(data: dict, json_path: Path, csv_path: Path, path: Path) -> None: + metadata = data["metadata"] + entries = summary_entries(data) + counts = Counter(entry["status"] for entry in entries) + order = status_order(data) + csv_link = markdown_link_target(csv_path, path) + json_display = display_path(json_path) + md_display = display_path(path) + csv_display = display_path(csv_path) + generator_display = display_path(Path(__file__).resolve()) + title = escape_markdown_text(metadata["title"]) + architecture = escape_markdown_text(metadata.get("architecture", "the architecture")) + download_label = escape_markdown_text( + metadata.get("csv_download_label", "Download rule coverage checklist CSV") + ) + include_sub_rule_id = has_sub_rules(data) + platforms = platform_names(data) + + lines = [ + f"# {title}", + "", + f"This document describes the {architecture} rule coverage checklist and status categories.", + "The coverage matrix itself is maintained in JSON form and generated as CSV so it", + "can be downloaded, filtered, and reviewed without duplicating the full table here.", + "", + "## Current Summary", + "", + "| Status | Count |", + "| --- | ---: |", + ] + for status in order: + lines.append(f"| `{status}` | {counts.get(status, 0)} |") + lines.extend( + [ + f"| `TOTAL` | {len(entries)} |", + "", + ] + ) + + if platforms: + lines.extend( + [ + "## Platform Information", + "", + "Platform coverage is tracked per rule in the generated CSV. Platform columns are left blank when the rule is not covered.", + "", + ] + ) + + lines.extend( + [ + "## Coverage Matrix", + "", + "The full checklist is available here:", + "", + f"[{download_label}]({csv_link})", + "", + "Gitiles may display the CSV as plain text. Download the file and open it in", + "Excel, LibreOffice, or another spreadsheet tool for filtering and offline review.", + "", + "The CSV contains these columns:", + "", + "| Column | Description |", + "| --- | --- |", + "| `Specification Rule ID` | Architecture rule ID. |", + *(["| `Sub Rule ID` | Optional sub-rule ID when a rule is split into smaller checks. |"] if include_sub_rule_id else []), + *([f"| `{escape_markdown_code(platform)}` | Whether ACS coverage exists for this platform; blank when not covered. |" for platform in platforms]), + "| `Status` | Current ACS coverage classification. |", + "| `Tests` | Direct ACS test file or indirect coverage source. |", + "| `Notes` | Short reasoning for the classification. |", + "", + "## Status Definitions", + "", + "| Status | Meaning |", + "| --- | --- |", + ] + ) + + for status in order: + details = data["status_definitions"][status] + lines.append( + f"| `{escape_markdown_code(status)}` | " + f"{escape_markdown_text(details['meaning'])} |" + ) + + lines.extend( + [ + "", + "## Maintenance", + "", + f"Update `{json_path.name}` when rule coverage changes, then regenerate this", + "Markdown file and the CSV with:", + "", + "```bash", + f"python3 {generator_display} --json {json_display}", + "```", + "", + "To choose explicit output paths:", + "", + "```bash", + f"python3 {generator_display} --json {json_display} --md {md_display} --csv {csv_display}", + "```", + "", + "Direct executable mappings must still be represented in `rule_metadata.c`.", + "Coverage detail is captured in `Notes` using prefixes such as `Direct:`,", + "`Indirect:`, `No ACS check required:`, `Not testable:`, and `Gap:`.", + "", + ] + ) + + path.write_text("\n".join(lines), encoding="utf-8") + + +def main() -> None: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument( + "--json", + type=Path, + required=True, + help="Input rule checklist JSON path.", + ) + parser.add_argument( + "--md", + type=Path, + help="Output Markdown path. Defaults to the input JSON path with .md suffix.", + ) + parser.add_argument( + "--csv", + type=Path, + help="Output CSV path. Defaults to the input JSON path with .csv suffix.", + ) + args = parser.parse_args() + + json_path = resolve_path(args.json) + md_path = resolve_output_path(args.md if args.md else json_path.with_suffix(".md")) + csv_path = resolve_output_path(args.csv if args.csv else json_path.with_suffix(".csv")) + + data = load_json(json_path) + validate(data) + write_csv(data, csv_path) + write_markdown(data, json_path, csv_path, md_path) + + +if __name__ == "__main__": + main() diff --git a/val/include/acs_common.h b/val/include/acs_common.h index 7016df57..c1892c52 100644 --- a/val/include/acs_common.h +++ b/val/include/acs_common.h @@ -79,6 +79,8 @@ typedef enum { /*These are the states a test can be in */ #define TEST_PENDING_VAL 0x3 +#define ACS_UINT32_MAX 0xFFFFFFFFU + #define CPU_NUM_BIT 32 #define CPU_NUM_MASK 0xFFFFFFFF diff --git a/val/include/acs_mpam.h b/val/include/acs_mpam.h index 3febde5e..a3f7ad0f 100644 --- a/val/include/acs_mpam.h +++ b/val/include/acs_mpam.h @@ -26,7 +26,6 @@ #define MPAM_VERSION_0_1 0x01 #define MPAM_VERSION_1_0 0x10 #define MPAM_VERSION_1_1 0x11 -#define MPAM_MSC_REGISTER_SPACE 0x2FFF // Last register access is 0x2000 + (127 * 32) + 31 /******************************************************************************* * MPAM system register bit definitions & constants @@ -196,4 +195,45 @@ uint32_t mpam006_entry(uint32_t num_pe); uint32_t mpam007_entry(uint32_t num_pe); uint32_t mpam008_entry(uint32_t num_pe); uint32_t mpam009_entry(uint32_t num_pe); + +uint32_t feat001_entry(uint32_t num_pe); + +uint32_t reg001_entry(uint32_t num_pe); +uint32_t reg004_entry(uint32_t num_pe); +uint32_t reg005_entry(uint32_t num_pe); +uint32_t reg006_entry(uint32_t num_pe); + +uint32_t partition001_entry(uint32_t num_pe); +uint32_t partition002_entry(uint32_t num_pe); +uint32_t partition004_entry(uint32_t num_pe); +uint32_t partition005_entry(uint32_t num_pe); +uint32_t partition006_entry(uint32_t num_pe); + +uint32_t mem001_entry(uint32_t num_pe); +uint32_t mem002_entry(uint32_t num_pe); +uint32_t mem003_entry(uint32_t num_pe); + +uint32_t monitor001_entry(uint32_t num_pe); +uint32_t monitor005_entry(uint32_t num_pe); +uint32_t monitor006_entry(uint32_t num_pe); +uint32_t monitor007_entry(uint32_t num_pe); +uint32_t monitor008_entry(uint32_t num_pe); + +uint32_t error001_entry(uint32_t num_pe); +uint32_t error003_entry(uint32_t num_pe); +uint32_t error005_entry(uint32_t num_pe); +uint32_t error007_entry(uint32_t num_pe); +uint32_t error008_entry(uint32_t num_pe); +uint32_t error009_entry(uint32_t num_pe); +uint32_t error010_entry(uint32_t num_pe); +uint32_t error011_entry(uint32_t num_pe); +uint32_t error012_entry(uint32_t num_pe); +uint32_t error013_entry(uint32_t num_pe); +uint32_t error014_entry(uint32_t num_pe); + +uint32_t intr001_entry(uint32_t num_pe); +uint32_t intr002_entry(uint32_t num_pe); +uint32_t intr003_entry(uint32_t num_pe); +uint32_t intr004_entry(uint32_t num_pe); +uint32_t intr005_entry(uint32_t num_pe); #endif /*__ACS_MPAM_H__ */ diff --git a/val/include/acs_mpam_reg.h b/val/include/acs_mpam_reg.h index b3e30f2a..59aa931f 100644 --- a/val/include/acs_mpam_reg.h +++ b/val/include/acs_mpam_reg.h @@ -34,7 +34,7 @@ /* Macro can be used write a particular bitfield with name##_MASK and name##_SHIFT already defined or declared for it without affecting other fields*/ #define BITFIELD_WRITE(reg_val, name, val) \ - ((reg_val & ~(name##_MASK << name##_SHIFT)) | (val << name##_SHIFT)) + (((reg_val) & ~((name##_MASK) << (name##_SHIFT))) | BITFIELD_SET(name, val)) /******************************************************************************* * MPAM memory mapped register offsets @@ -193,7 +193,7 @@ BITFIELD_DECL(uint32_t, MPAMCFG_DIS_NFU, 31, 31) /* MS Monitor Counter Max values */ #define MSMON_COUNT_63BIT 0x7fffffffffffffff -#define MSMON_COUNT_44BIT 0x1FFFFFFFFFFF +#define MSMON_COUNT_44BIT 0xFFFFFFFFFFFULL #define MSMON_COUNT_31BIT 0x7FFFFFFF /* MPAMF_ESR bit values */ @@ -236,6 +236,7 @@ BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_INTR_L, 14, 14) BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_STATUS_L, 15, 15) BITFIELD_DECL(uint32_t, MBWU_CTL_MATCH_PARTID, 16, 16) BITFIELD_DECL(uint32_t, MBWU_CTL_MATCH_PMG, 17, 17) +BITFIELD_DECL(uint32_t, MBWU_CTL_SCLEN, 19, 19) BITFIELD_DECL(uint32_t, MBWU_CTL_SUBTYPE, 23, 20) BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_FRZ, 24, 24) BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_INTR, 25, 25) diff --git a/val/include/rule_based_execution.h b/val/include/rule_based_execution.h index 218eaf76..a4399a3e 100644 --- a/val/include/rule_based_execution.h +++ b/val/include/rule_based_execution.h @@ -85,6 +85,11 @@ typedef struct { PFDI_LEVEL_e level; } pfdi_rule_entry_t; +typedef struct { + RULE_ID_e rule_id; + MPAM_VERSION_e version; +} mpam_rule_entry_t; + /* ---------------------------- Helper functions declarations ---------------------------------- */ void quick_sort_rule_list(RULE_ID_e *rule_list, uint32_t list_size); uint32_t check_module_init(MODULE_NAME_e module_id); @@ -109,11 +114,13 @@ extern const sbsa_rule_entry_t sbsa_rule_list[]; extern const pcbsa_rule_entry_t pcbsa_rule_list[]; extern const vbsa_rule_entry_t vbsa_rule_list[]; extern const pfdi_rule_entry_t pfdi_rule_list[]; +extern const mpam_rule_entry_t mpam_rule_list[]; extern const uint32_t bsa_rule_list_len; extern const uint32_t sbsa_rule_list_len; extern const uint32_t pcbsa_rule_list_len; extern const uint32_t vbsa_rule_list_len; extern const uint32_t pfdi_rule_list_len; +extern const uint32_t mpam_rule_list_len; /* ------------------------------------ VAL APIs ------------------------------------------------*/ uint32_t filter_rule_list_by_cli(acs_run_request_t *ctx); diff --git a/val/include/rule_based_execution_enum.h b/val/include/rule_based_execution_enum.h index 3791881a..9b1af50e 100644 --- a/val/include/rule_based_execution_enum.h +++ b/val/include/rule_based_execution_enum.h @@ -310,6 +310,221 @@ typedef enum { S_L7MP_05, S_L7MP_08, + /* SYS-MPAM rules */ + BDJXQ, + DDGSM, + RBCMK, + CFXGZ, + FXVBB, + LRZGD, + PBSTK, + KXMHB, + CZHSY, + RBWRS, + QKQCF, + CZSZX, + NVNHD, + SLJDR, + VNVMD, + SJFGX, + YPHLH, + RZCWR, + MRWWK, + XPPBS, + CWTSC, + JWKJD, + SGBFN, + ZTFBQ, + JGWSM, + LRNPR, + VBHPB, + WZXPM, + CBBRW, + CNQCS, + BHHCR, + BSLZQ, + WBZST, + YWPPT, + BNKHP, + KFDFD, + XRQHH, + VKQKB, + TTSLQ, + RGSJV, + MFRGP, + CYKPC, + KPNNZ, + JXRZM, + RHYKB, + LQQJN, + KBJPW, + YBYPZ, + CNGYT, + HHQWY, + WSXSL, + YQBMW, + YXZFG, + DQNFB, + YGZYL, + PLZWM, + DNNTB, + LXXDB, + MRZLG, + NPVVN, + HSFKH, + XRHKL, + GDMQZ, + MMXWZ, + QFCTM, + CZMFT, + XDZGT, + HLHYS, + GVCBB, + KWGHQ, + TZWJG, + VFJMZ, + WFQFS, + GMCWW, + CSLHH, + QFRFQ, + RNSLZ, + NJXHP, + XPPGG, + ZVTKX, + RLHRV, + ZRSRZ, + WMPLL, + LPLMM, + BDRCM, + ZHBXH, + SWNLN, + VZBFH, + CXZDR, + FRTVY, + DPZKC, + DKYDB, + GYMDB, + CFHQL, + HVRZS, + WKZBJ, + BPRDL, + WRXBV, + NWVFK, + PKRGZ, + VWHYW, + PWSWQ, + XSYFH, + ZQXQL, + CMZNL, + PXSBS, + ZDTLN, + ZFCRG, + TKBDC, + MSPZM, + JJKQP, + NGDBL, + MQRPH, + RZDSR, + MBNHC, + JPLMZ, + DQTTD, + RNWBS, + GFYDF, + WCQKV, + ZGGMX, + TMCXJ, + YFMQP, + DLSGF, + WHJQG, + VLSJS, + RYRQJ, + QGXSZ, + VJDKF, + DSCQB, + FWCFZ, + PVNHR, + KCWDZ, + XLWYW, + GKWNB, + LRTGP, + NXKSF, + FVFYC, + ZTXDS, + VBZTW, + FZHDC, + YFVPY, + NKTBN, + NWKJR, + SQSMV, + WQJKV, + XZXVK, + NDMMK, + VBBTL, + XSTRM, + JCNST, + DFWFP, + GNQFY, + MGGJW, + HXNGD, + RPGBQ, + MTGGZ, + DYNFP, + WHSLQ, + GVBGS, + QBKDG, + DLSCZ, + ZWRQW, + VKKDP, + XTQZR, + XDCDL, + JMLNM, + XMLDN, + VMTBP, + WXKWK, + MGXDK, + HJRZC, + SQTSJ, + VZWYW, + PNPQQ, + SJFMB, + VYLZC, + QBQJG, + PFNBV, + CZZZK, + HVNKJ, + TMMMD, + QDSPY, + PPJSM, + GLPPK, + NRGQD, + KVGWS, + KVHTZ, + ZRDMM, + YLCVK, + YJCDR, + YVSNK, + JLYJJ, + MBDJF, + LVCGQ, + DMKKT, + VTFQK, + CTGKD, + RDMVJ, + KNNBY, + ZPWLC, + DYDFT, + HXLMF, + QCYPH, + FLWNK, + GTKCX, + DFBBW, + FYTQL, + KZBWG, + YCBKB, + TVYHS, + RJFKG, + FKNKB, + /* ETE */ ETE_01, ETE_02, @@ -918,6 +1133,40 @@ typedef enum { MPAM005_ENTRY, MPAM006_ENTRY, MPAM007_ENTRY, + FEAT001_ENTRY, + REG001_ENTRY, + REG004_ENTRY, + REG005_ENTRY, + REG006_ENTRY, + PARTITION001_ENTRY, + PARTITION002_ENTRY, + PARTITION004_ENTRY, + PARTITION005_ENTRY, + PARTITION006_ENTRY, + MONITOR007_ENTRY, + MONITOR008_ENTRY, + ERROR001_ENTRY, + ERROR003_ENTRY, + ERROR005_ENTRY, + ERROR008_ENTRY, + ERROR010_ENTRY, + ERROR013_ENTRY, + INTR001_ENTRY, + INTR002_ENTRY, + INTR003_ENTRY, + INTR005_ENTRY, + MONITOR001_ENTRY, + ERROR009_ENTRY, + ERROR012_ENTRY, + MEM001_ENTRY, + MEM002_ENTRY, + MEM003_ENTRY, + INTR004_ENTRY, + MONITOR005_ENTRY, + ERROR014_ENTRY, + ERROR007_ENTRY, + ERROR011_ENTRY, + MONITOR006_ENTRY, ETE001_ENTRY, ETE002_ENTRY, ETE003_ENTRY, @@ -1035,6 +1284,10 @@ typedef enum { NV_STORE, SECURITY, TME, + MPAM_CACHE, + MPAM_REG, + MPAM_ERROR, + MPAM_MBWU, MODULE_ID_SENTINEL /* need to be in last */ } MODULE_NAME_e; @@ -1085,6 +1338,12 @@ typedef enum { PFDI_LEVEL_SENTINEL /* Keep last */ } PFDI_LEVEL_e; +/* MPAM architecture versions enum */ +typedef enum { + MPAM_VERSION_B_c = 1, + MPAM_VERSION_SENTINEL /* Keep last */ +} MPAM_VERSION_e; + /* Software views enum for BSA */ typedef enum { SW_OS, @@ -1106,7 +1365,8 @@ typedef enum { ARCH_SBSA, ARCH_PCBSA, ARCH_VBSA, - ARCH_PFDI + ARCH_PFDI, + ARCH_SYS_MPAM } ARCH_SEL_e; /* Level filter mode for CLI selection */ diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 79b17dfe..034c95a3 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -789,10 +789,10 @@ typedef enum { } MPAM_MODULE_ID_e; // Module entry functions. -uint32_t val_mpam_execute_register_tests(void); -uint32_t val_mpam_execute_error_tests(void); -uint32_t val_mpam_execute_cache_tests(void); -uint32_t val_mpam_execute_membw_tests(void); +uint32_t val_mpam_execute_register_tests(uint32_t num_pe); +uint32_t val_mpam_execute_error_tests(uint32_t num_pe); +uint32_t val_mpam_execute_cache_tests(uint32_t num_pe); +uint32_t val_mpam_execute_membw_tests(uint32_t num_pe); // VAL API prototypes uint32_t val_mpam_msc_reset_errcode(uint32_t msc_index); @@ -816,58 +816,58 @@ void val_mpam_mbwu_wait_for_update(uint32_t msc_index); uint32_t val_mpam_get_msc_device_info(uint32_t msc_index, uint32_t *device_id, uint32_t *its_id); // Register tests entry calls -uint32_t reg001_entry(void); -uint32_t reg002_entry(void); -uint32_t reg003_entry(void); -uint32_t reg004_entry(void); -uint32_t reg005_entry(void); -uint32_t reg006_entry(void); +uint32_t reg001_entry(uint32_t num_pe); +uint32_t reg002_entry(uint32_t num_pe); +uint32_t reg003_entry(uint32_t num_pe); +uint32_t reg004_entry(uint32_t num_pe); +uint32_t reg005_entry(uint32_t num_pe); +uint32_t reg006_entry(uint32_t num_pe); // Memory Bandwidth partitioning tests entry calls -uint32_t mem001_entry(void); -uint32_t mem002_entry(void); -uint32_t mem003_entry(void); +uint32_t mem001_entry(uint32_t num_pe); +uint32_t mem002_entry(uint32_t num_pe); +uint32_t mem003_entry(uint32_t num_pe); // Error and Interrupt tests entry calls -uint32_t error001_entry(void); -uint32_t error002_entry(void); -uint32_t error003_entry(void); -uint32_t error004_entry(void); -uint32_t error005_entry(void); -uint32_t error006_entry(void); -uint32_t error007_entry(void); -uint32_t error008_entry(void); -uint32_t error009_entry(void); -uint32_t error010_entry(void); -uint32_t error011_entry(void); -uint32_t error012_entry(void); -uint32_t error013_entry(void); -uint32_t error014_entry(void); -uint32_t intr001_entry(void); -uint32_t intr002_entry(void); -uint32_t intr003_entry(void); -uint32_t intr004_entry(void); -uint32_t intr005_entry(void); -uint32_t intr006_entry(void); +uint32_t error001_entry(uint32_t num_pe); +uint32_t error002_entry(uint32_t num_pe); +uint32_t error003_entry(uint32_t num_pe); +uint32_t error004_entry(uint32_t num_pe); +uint32_t error005_entry(uint32_t num_pe); +uint32_t error006_entry(uint32_t num_pe); +uint32_t error007_entry(uint32_t num_pe); +uint32_t error008_entry(uint32_t num_pe); +uint32_t error009_entry(uint32_t num_pe); +uint32_t error010_entry(uint32_t num_pe); +uint32_t error011_entry(uint32_t num_pe); +uint32_t error012_entry(uint32_t num_pe); +uint32_t error013_entry(uint32_t num_pe); +uint32_t error014_entry(uint32_t num_pe); +uint32_t intr001_entry(uint32_t num_pe); +uint32_t intr002_entry(uint32_t num_pe); +uint32_t intr003_entry(uint32_t num_pe); +uint32_t intr004_entry(uint32_t num_pe); +uint32_t intr005_entry(uint32_t num_pe); +uint32_t intr006_entry(uint32_t num_pe); /* Cache Tests */ -uint32_t partition001_entry(void); -uint32_t partition002_entry(void); -uint32_t partition003_entry(void); -uint32_t partition004_entry(void); -uint32_t partition005_entry(void); -uint32_t partition006_entry(void); - -uint32_t feat001_entry(void); // MPAM PARTID EN/DIS feature check test - -uint32_t monitor001_entry(void); -uint32_t monitor002_entry(void); -uint32_t monitor003_entry(void); -uint32_t monitor004_entry(void); -uint32_t monitor005_entry(void); -uint32_t monitor006_entry(void); -uint32_t monitor007_entry(void); -uint32_t monitor008_entry(void); +uint32_t partition001_entry(uint32_t num_pe); +uint32_t partition002_entry(uint32_t num_pe); +uint32_t partition003_entry(uint32_t num_pe); +uint32_t partition004_entry(uint32_t num_pe); +uint32_t partition005_entry(uint32_t num_pe); +uint32_t partition006_entry(uint32_t num_pe); + +uint32_t feat001_entry(uint32_t num_pe); // MPAM PARTID EN/DIS feature check test + +uint32_t monitor001_entry(uint32_t num_pe); +uint32_t monitor002_entry(uint32_t num_pe); +uint32_t monitor003_entry(uint32_t num_pe); +uint32_t monitor004_entry(uint32_t num_pe); +uint32_t monitor005_entry(uint32_t num_pe); +uint32_t monitor006_entry(uint32_t num_pe); +uint32_t monitor007_entry(uint32_t num_pe); +uint32_t monitor008_entry(uint32_t num_pe); // Accessing system registers from .S -> can be moved to respective .h uint64_t arm64_write_sp(uint64_t write_data); diff --git a/val/src/acs_mpam.c b/val/src/acs_mpam.c index ae55042b..a2d79f05 100644 --- a/val/src/acs_mpam.c +++ b/val/src/acs_mpam.c @@ -189,23 +189,9 @@ val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) msc_entry = &g_mpam_info_table->msc_node[0]; for (i = 0; i < g_mpam_info_table->msc_count; i++, msc_entry = MPAM_NEXT_MSC(msc_entry)) { if (msc_index == i) { - if (rsrc_index > msc_entry->rsrc_count - 1) { - val_print(ERROR, - "\n Invalid MSC resource index = 0x%lx for", rsrc_index); - val_print(ERROR, "MSC index = 0x%lx ", msc_index); - return MPAM_INVALID_INFO; - } switch (type) { case MPAM_MSC_RSRC_COUNT: return msc_entry->rsrc_count; - case MPAM_MSC_RSRC_RIS: - return msc_entry->rsrc_node[rsrc_index].ris_index; - case MPAM_MSC_RSRC_TYPE: - return msc_entry->rsrc_node[rsrc_index].locator_type; - case MPAM_MSC_RSRC_DESC1: - return msc_entry->rsrc_node[rsrc_index].descriptor1; - case MPAM_MSC_RSRC_DESC2: - return msc_entry->rsrc_node[rsrc_index].descriptor2; case MPAM_MSC_BASE_ADDR: return msc_entry->msc_base_addr; case MPAM_MSC_ADDR_LEN: @@ -224,6 +210,26 @@ val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) return msc_entry->identifier; case MPAM_MSC_INTERFACE_TYPE: return msc_entry->intrf_type; + default: + break; + } + + if (rsrc_index >= msc_entry->rsrc_count) { + val_print(ERROR, + "\n Invalid MSC resource index = 0x%lx for", rsrc_index); + val_print(ERROR, "MSC index = 0x%lx ", msc_index); + return MPAM_INVALID_INFO; + } + + switch (type) { + case MPAM_MSC_RSRC_RIS: + return msc_entry->rsrc_node[rsrc_index].ris_index; + case MPAM_MSC_RSRC_TYPE: + return msc_entry->rsrc_node[rsrc_index].locator_type; + case MPAM_MSC_RSRC_DESC1: + return msc_entry->rsrc_node[rsrc_index].descriptor1; + case MPAM_MSC_RSRC_DESC2: + return msc_entry->rsrc_node[rsrc_index].descriptor2; default: val_print(ERROR, "\n This MPAM info option for type %d is not supported", type); @@ -1068,6 +1074,7 @@ val_mpam_memory_configure_ris_sel(uint32_t msc_index, uint32_t rsrc_index) field to be 0 */ data = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MON_SEL); data = BITFIELD_WRITE(data, MON_SEL_RIS, ris_index); + data = BITFIELD_WRITE(data, MON_SEL_MON_SEL, 0); val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MON_SEL, data); /* configure MPAMCFG_PART_SEL.RIS field and write MPAMCFG_PART_SEL. @@ -1102,8 +1109,10 @@ val_mpam_memory_configure_mbwumon(uint32_t msc_index) /* disable monitor instance before configuration */ val_mpam_memory_mbwumon_disable(msc_index); - /* configure monitor ctrl reg for default partid and default pmg */ - data = BITFIELD_SET(MBWU_CTL_MATCH_PARTID, 1) | BITFIELD_SET(MBWU_CTL_MATCH_PMG, 1); + /* configure matching controls while preserving other monitor settings */ + data = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); + data = BITFIELD_WRITE(data, MBWU_CTL_MATCH_PARTID, 1); + data = BITFIELD_WRITE(data, MBWU_CTL_MATCH_PMG, 1); val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MBWU_CTL, data); data = 0; @@ -1181,6 +1190,7 @@ val_mpam_memory_mbwumon_read_count(uint32_t msc_index) uint64_t count = MPAM_MON_NOT_READY; uint64_t msmon_mbwu_l; uint32_t msmon_mbwu; + uint32_t mbwu_ctl; uint32_t mbwumon_idr = val_mpam_mmr_read(msc_index, REG_MPAMF_MBWUMON_IDR); /* Check HAS_LONG to determine if MSMON_MBWU_L is implemented. */ @@ -1204,7 +1214,9 @@ val_mpam_memory_mbwumon_read_count(uint32_t msc_index) if (BITFIELD_READ(MSMON_MBWU_NRDY, msmon_mbwu) == 0) { count = BITFIELD_READ(MSMON_MBWU_VALUE, msmon_mbwu); /* shift the count if scaling is enabled */ - count = count << BITFIELD_READ(MBWUMON_IDR_SCALE, mbwumon_idr); + mbwu_ctl = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); + if (BITFIELD_READ(MBWU_CTL_SCLEN, mbwu_ctl)) + count = count << BITFIELD_READ(MBWUMON_IDR_SCALE, mbwumon_idr); } } return(count); @@ -1221,11 +1233,26 @@ val_mpam_memory_mbwumon_read_count(uint32_t msc_index) void val_mpam_memory_mbwumon_reset(uint32_t msc_index) { - /*if MSMON_MBWU_L is implemented*/ + uint32_t mbwu_ctl; + uint32_t monitor_enabled; + + mbwu_ctl = val_mpam_mmr_read(msc_index, REG_MSMON_CFG_MBWU_CTL); + monitor_enabled = BITFIELD_READ(MBWU_CTL_EN, mbwu_ctl); + + if (monitor_enabled) { + val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MBWU_CTL, + BITFIELD_WRITE(mbwu_ctl, MBWU_CTL_EN, 0)); + val_mem_issue_dsb(); + } + + val_mpam_mmr_write(msc_index, REG_MSMON_MBWU, 0); if (val_mpam_mbwu_supports_long(msc_index)) val_mpam_mmr_write64(msc_index, REG_MSMON_MBWU_L, 0); - else - val_mpam_mmr_write(msc_index, REG_MSMON_MBWU, 0); + + if (monitor_enabled) + val_mpam_mmr_write(msc_index, REG_MSMON_CFG_MBWU_CTL, mbwu_ctl); + + val_mem_issue_dsb(); } @@ -1300,16 +1327,18 @@ memory_map_msc(void) { uint32_t msc_index; uint32_t intrf_type; + uint32_t msc_addr_len; uint64_t msc_base; uint32_t msc_node_cnt = val_mpam_get_msc_count(); for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { msc_base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + msc_addr_len = val_mpam_get_info(MPAM_MSC_ADDR_LEN, msc_index, 0); intrf_type = val_mpam_get_info(MPAM_MSC_INTERFACE_TYPE, msc_index, 0); /* If interface is MMIO, make sure the MSC registers are mapped in PE MMU */ if (intrf_type == MPAM_INTERFACE_TYPE_MMIO) { - val_mmu_update_entry(msc_base, MPAM_MSC_REGISTER_SPACE, DEVICE_nGnRnE); + val_mmu_update_entry(msc_base, msc_addr_len, DEVICE_nGnRnE); /* If interface is PCC, make sure the Doorbell registers, etc. are mapped */ } else if (intrf_type == MPAM_INTERFACE_TYPE_PCC) { @@ -1482,7 +1511,10 @@ val_hmat_create_info_table(uint64_t *hmat_info_table) void val_hmat_free_info_table(void) { - pal_mem_free_aligned((void *)g_hmat_info_table); + if (g_hmat_info_table != NULL) { + pal_mem_free_aligned((void *)g_hmat_info_table); + g_hmat_info_table = NULL; + } } /** @@ -1520,7 +1552,10 @@ val_srat_create_info_table(uint64_t *srat_info_table) void val_srat_free_info_table(void) { - pal_mem_free_aligned((void *)g_srat_info_table); + if (g_srat_info_table != NULL) { + pal_mem_free_aligned((void *)g_srat_info_table); + g_srat_info_table = NULL; + } } /** @@ -1597,6 +1632,68 @@ val_mpam_get_bwa_wd(uint32_t msc_index) { return BITFIELD_READ(BWA_WD, val_mpam_mmr_read(msc_index, REG_MPAMF_MBW_IDR)); } + +static uint16_t +mpam_encode_fraction(uint32_t width, uint32_t percentage, uint8_t subtract_one) +{ + uint32_t fraction; + uint32_t max_fraction; + + if (width > 16) { + val_print(WARN, "\n Fractional width %d exceeds 16; clamping", width); + width = 16; + } + if (percentage > 100) { + val_print(WARN, "\n Percentage %d exceeds 100; clamping", percentage); + percentage = 100; + } + if (width == 0) + return 0; + + max_fraction = (1U << width) - 1U; + fraction = ((1U << width) * percentage) / 100; + if (subtract_one && fraction != 0) + fraction--; + if (fraction > max_fraction) + fraction = max_fraction; + + return (uint16_t)(fraction << (16 - width)); +} + +static void +mpam_program_bitmap(uint32_t msc_index, uint32_t reg, uint32_t width, + uint32_t max_width, uint32_t percentage) +{ + uint32_t bit_count; + uint32_t total_words; + uint32_t word; + uint32_t word_value; + + if (width > max_width) { + val_print(WARN, "\n Bitmap width %d exceeds supported maximum; clamping", width); + width = max_width; + } + if (percentage > 100) { + val_print(WARN, "\n Percentage %d exceeds 100; clamping", percentage); + percentage = 100; + } + + bit_count = (width * percentage) / 100; + total_words = (width + 31) / 32; + + for (word = 0; word < total_words; word++) { + if (bit_count >= 32) + word_value = ACS_UINT32_MAX; + else if (bit_count != 0) + word_value = (1U << bit_count) - 1U; + else + word_value = 0; + + val_mpam_mmr_write(msc_index, reg + (word * sizeof(uint32_t)), word_value); + bit_count = (bit_count > 32) ? bit_count - 32 : 0; + } +} + /** @brief This API Configures CPOR settings for given MSC Prerequisite - If MSC supports RIS, Resource instance should be @@ -1612,10 +1709,7 @@ val_mpam_get_bwa_wd(uint32_t msc_index) void val_mpam_configure_cpor(uint32_t msc_index, uint16_t partid, uint32_t cpbm_percentage) { - uint16_t index; - uint32_t unset_bitmask; - uint32_t num_unset_bits; - uint16_t num_cpbm_bits; + uint32_t num_cpbm_bits; uint32_t data; /* Get CPBM width */ @@ -1628,19 +1722,8 @@ val_mpam_configure_cpor(uint32_t msc_index, uint16_t partid, uint32_t cpbm_perce data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); - /* - * Configure CPBM register to have a 1 in cpbm_percentage - * bits in the overall CPBM_WD bit positions - */ - num_cpbm_bits = (num_cpbm_bits * cpbm_percentage) / 100 ; - for (index = 0; index < (num_cpbm_bits - 31) && index < MAX_CPBM_WIDTH; index += 32) - val_mpam_mmr_write(msc_index, REG_MPAMCFG_CPBM + (index / 8), CPOR_BITMAP_DEF_VAL); - - /* Unset bits from above step are set */ - num_unset_bits = num_cpbm_bits - index; - unset_bitmask = (1 << num_unset_bits) - 1; - if (unset_bitmask) - val_mpam_mmr_write(msc_index, REG_MPAMCFG_CPBM + (index / 8), unset_bitmask); + mpam_program_bitmap(msc_index, REG_MPAMCFG_CPBM, num_cpbm_bits, + MAX_CPBM_WIDTH, cpbm_percentage); /* Issue a DSB instruction */ val_mem_issue_dsb(); @@ -1668,7 +1751,7 @@ void val_mpam_configure_ccap(uint32_t msc_index, uint16_t partid, uint32_t data; num_fractional_bits = val_mpam_get_cmax_wd(msc_index); - fixed_point_fraction = ((1 << num_fractional_bits) * ccap_percentage / 100) - 1; + fixed_point_fraction = mpam_encode_fraction(num_fractional_bits, ccap_percentage, 1); /* Select the PARTID to configure capacity partition parameters */ data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); @@ -1681,8 +1764,8 @@ void val_mpam_configure_ccap(uint32_t msc_index, uint16_t partid, * Use num_fractional_bits fixed-point representation */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_CMAX, - (softlim << MPAMCFG_CMAX_SOFTLIM_SHIFT) | - ((fixed_point_fraction << (16 - num_fractional_bits)) & 0xFFFF)); + ((uint32_t)softlim << MPAMCFG_CMAX_SOFTLIM_SHIFT) | + fixed_point_fraction); val_mem_issue_dsb(); return; @@ -1707,18 +1790,19 @@ void val_mpam_configure_cassoc(uint32_t msc_index, uint16_t partid, uint32_t data; num_fractional_bits = val_mpam_get_cassoc_wd(msc_index); - fixed_point_fraction = ((1 << num_fractional_bits) * cassoc_percentage / 100) - 1; + fixed_point_fraction = mpam_encode_fraction(num_fractional_bits, cassoc_percentage, 1); /* Select the PARTID to configure CASSOC partition parameters */ data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); - val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, (data | partid)); + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); /* * Configure the CASSOC register for the cache associativity control settings. * Use num_fractional_bits fixed-point representation */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_CASSOC, - (fixed_point_fraction << (16 - num_fractional_bits)) & 0xFFFF); + fixed_point_fraction); val_mem_issue_dsb(); return; @@ -1739,27 +1823,22 @@ void val_mpam_configure_cmin(uint32_t msc_index, uint16_t partid, uint32_t cmin_ uint8_t num_fractional_bits; uint16_t fixed_point_fraction; + uint32_t data; num_fractional_bits = val_mpam_get_cmax_wd(msc_index); - if (num_fractional_bits > 16) { - val_print(ERROR, "\n Number of fractional bits = %d not permitted", - num_fractional_bits); - num_fractional_bits = 16; - } - - fixed_point_fraction = ((1 << num_fractional_bits) * cmin_percentage / 100); - if (fixed_point_fraction != 0) - fixed_point_fraction -= 1; + fixed_point_fraction = mpam_encode_fraction(num_fractional_bits, cmin_percentage, 0); /* Select the PARTID to configure capacity partition parameters */ - val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, partid); + data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); /* * Configure the CMIN register - min cache capacity to be allocated for the PARTID. * Use num_fractional_bits fixed-point representation */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_CMIN, - ((fixed_point_fraction << (16 - num_fractional_bits)) & 0xFFFF)); + fixed_point_fraction); val_mem_issue_dsb(); return; @@ -1779,30 +1858,18 @@ void val_mpam_configure_mbwpbm(uint32_t msc_index, uint16_t partid, uint32_t mbwpbm_percentage) { - uint16_t index; - uint32_t unset_bitmask; - uint32_t num_unset_bits; - uint16_t num_mbwpbm_bits; + uint32_t num_mbwpbm_bits; + uint32_t data; num_mbwpbm_bits = val_mpam_get_mbwpbm_width(msc_index); /* Select the PARTID to configure portion partition parameters */ - val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, partid); - - /* - * Configure MBWPBM register to have a 1 in mbwpbm_percentage - * bits in the overall MBWBM_WD bit positions - */ - num_mbwpbm_bits = num_mbwpbm_bits * mbwpbm_percentage / 100; - for (index = 0; index < (num_mbwpbm_bits - 31) && index < MAX_BWPBM_WIDTH; index += 32) { - val_mpam_mmr_write(msc_index, REG_MPAMCFG_MBW_PBM + (index / 8), MBWPOR_BITMAP_DEF_VAL); - } + data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); - num_unset_bits = num_mbwpbm_bits - index; - unset_bitmask = (1 << num_unset_bits) - 1; - if (unset_bitmask) { - val_mpam_mmr_write(msc_index, REG_MPAMCFG_MBW_PBM + (index / 8), unset_bitmask); - } + mpam_program_bitmap(msc_index, REG_MPAMCFG_MBW_PBM, num_mbwpbm_bits, + MAX_BWPBM_WIDTH, mbwpbm_percentage); val_mem_issue_dsb(); return; @@ -1821,19 +1888,22 @@ void val_mpam_msc_configure_mbwmin(uint32_t msc_index, uint16_t partid, uint32_t { uint8_t num_fractional_bits; uint16_t fixed_point_fraction; + uint32_t data; num_fractional_bits = val_mpam_get_bwa_wd(msc_index); - fixed_point_fraction = ((1 << num_fractional_bits) * mbwmin_percentage / 100) - 1; + fixed_point_fraction = mpam_encode_fraction(num_fractional_bits, mbwmin_percentage, 0); /* Select the PARTID to configure minimum bandwidth limit parameters */ - val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, partid); + data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); /* * Configure the MBW_MIN register for minimum bandwidth limit. * Use num_fractional_bits fixed-point representation */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_MBW_MIN, - (fixed_point_fraction << (16 - num_fractional_bits)) & 0xFFFF); + fixed_point_fraction); /* Issue a DSB instruction */ val_mem_issue_dsb(); @@ -1855,20 +1925,23 @@ void val_mpam_msc_configure_mbwmax(uint32_t msc_index, uint16_t partid, { uint8_t num_fractional_bits; uint16_t fixed_point_fraction; + uint32_t data; num_fractional_bits = val_mpam_get_bwa_wd(msc_index); - fixed_point_fraction = ((1 << num_fractional_bits) * mbwmax_percentage / 100) - 1; + fixed_point_fraction = mpam_encode_fraction(num_fractional_bits, mbwmax_percentage, 1); /* Select the PARTID to configure maximum bandwidth partition parameters */ - val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, partid); + data = val_mpam_mmr_read(msc_index, REG_MPAMCFG_PART_SEL); + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mpam_mmr_write(msc_index, REG_MPAMCFG_PART_SEL, data); /* * Configure the MBW_MAX register for maximum bandwidth limit. * Use num_fractional_bits fixed-point representation */ val_mpam_mmr_write(msc_index, REG_MPAMCFG_MBW_MAX, - (hardlim << MPAMCFG_MBW_MAX_HARDLIM_SHIFT) | - ((fixed_point_fraction << (16 - num_fractional_bits)) & 0xFFFF)); + ((uint32_t)hardlim << MPAMCFG_MBW_MAX_HARDLIM_SHIFT) | + fixed_point_fraction); /* Issue a DSB instruction */ val_mem_issue_dsb(); @@ -1993,7 +2066,7 @@ val_mpam_csumon_disable(uint32_t msc_index) } /** - @brief This API reads the CSU montior counter value. + @brief This API waits for MAX_NRDY and reads the CSU monitor counter value. Prerequisite - val_mpam_configure_csu_mon, This API can be called only after configuring CSU monitor. @@ -2005,12 +2078,17 @@ uint32_t val_mpam_read_csumon(uint32_t msc_index) { uint32_t count; + uint64_t nrdy_timeout; + + /* Avoid repeated MMIO polling while allowing the monitor update to complete. */ + nrdy_timeout = val_mpam_get_info(MPAM_MSC_NRDY, msc_index, 0); + if ((nrdy_timeout != 0) && (nrdy_timeout != MPAM_INVALID_INFO)) + val_time_delay_ms(nrdy_timeout); + + count = val_mpam_mmr_read(msc_index, REG_MSMON_CSU); + if (BITFIELD_READ(MSMON_CSU_NRDY, count) == 0) + return BITFIELD_READ(MSMON_CSU_VALUE, count); - if (BITFIELD_READ(MSMON_CSU_NRDY, val_mpam_mmr_read(msc_index, REG_MSMON_CSU)) == 0) { - count = BITFIELD_READ(MSMON_CSU_VALUE, - val_mpam_mmr_read(msc_index, REG_MSMON_CSU)); - return count; - } return 0; } @@ -2444,14 +2522,14 @@ uint32_t val_mpam_program_el2(uint16_t partid, uint8_t pmg) @param enable - 1 to enable, 0 to disable PARTID @param nfu_flag - No future Use if PARTID is to be disabled @param partid - PARTID to be enabled/disabled - @return 1 on success, 0 on failure. + @return 0 on success, 1 on failure. */ uint32_t val_mpam_msc_endis_partid(uint32_t msc_index, bool enable, bool nfu_flag, uint16_t partid) { /* Check if the PARTID is valid */ - if (partid >= val_mpam_get_max_partid(msc_index)) { + if (partid > val_mpam_get_max_partid(msc_index)) { val_print(ERROR, "\n PARTID value (0x%x)", partid); val_print(ERROR, " specified more than MSC supported value (0x%x)", val_mpam_get_max_partid(msc_index)); @@ -2670,10 +2748,12 @@ val_mpam_msc_enable_msi(uint32_t msc_index, uint32_t is_oflow_msi) uint32_t attr; if (is_oflow_msi) { - attr = BITFIELD_SET(OFLOW_MSI_ATTR_MSIEN, 1); + attr = val_mpam_mmr_read(msc_index, REG_MSMON_OFLOW_MSI_ATTR); + attr = BITFIELD_WRITE(attr, OFLOW_MSI_ATTR_MSIEN, 1); val_mpam_mmr_write(msc_index, REG_MSMON_OFLOW_MSI_ATTR, attr); } else { - attr = BITFIELD_SET(ERR_MSI_ATTR_MSIEN, 1); + attr = val_mpam_mmr_read(msc_index, REG_MPAMF_ERR_MSI_ATTR); + attr = BITFIELD_WRITE(attr, ERR_MSI_ATTR_MSIEN, 1); val_mpam_mmr_write(msc_index, REG_MPAMF_ERR_MSI_ATTR, attr); } diff --git a/val/src/mpam_execute_test.c b/val/src/mpam_execute_test.c index f9a958d5..ddc15aa2 100644 --- a/val/src/mpam_execute_test.c +++ b/val/src/mpam_execute_test.c @@ -29,7 +29,7 @@ @return Consolidated status of all the tests run. **/ uint32_t -val_mpam_execute_error_tests(void) +val_mpam_execute_error_tests(uint32_t num_pe) { uint32_t status, i; @@ -52,24 +52,24 @@ val_mpam_execute_error_tests(void) val_print_test_start("ERROR"); g_curr_module = 1 << ERROR_MODULE; - status = error001_entry(); - status |= error002_entry(); - status |= error003_entry(); - status |= error004_entry(); - status |= error005_entry(); - status |= error006_entry(); - status |= error007_entry(); - status |= error008_entry(); - status |= error009_entry(); - status |= error010_entry(); - status |= error011_entry(); - status |= error012_entry(); - status |= error013_entry(); - status |= error014_entry(); - status |= intr001_entry(); - status |= intr002_entry(); - status |= intr003_entry(); - status |= intr004_entry(); + status = error001_entry(num_pe); + status |= error002_entry(num_pe); + status |= error003_entry(num_pe); + status |= error004_entry(num_pe); + status |= error005_entry(num_pe); + status |= error006_entry(num_pe); + status |= error007_entry(num_pe); + status |= error008_entry(num_pe); + status |= error009_entry(num_pe); + status |= error010_entry(num_pe); + status |= error011_entry(num_pe); + status |= error012_entry(num_pe); + status |= error013_entry(num_pe); + status |= error014_entry(num_pe); + status |= intr001_entry(num_pe); + status |= intr002_entry(num_pe); + status |= intr003_entry(num_pe); + status |= intr004_entry(num_pe); /* Setup ITS for MSI Tests */ if (g_its_init != 1) { @@ -83,8 +83,8 @@ val_mpam_execute_error_tests(void) } if (g_its_init) { - status |= intr005_entry(); - status |= intr006_entry(); + status |= intr005_entry(num_pe); + status |= intr006_entry(num_pe); } val_print_test_end(status, "ERROR"); @@ -101,7 +101,7 @@ val_mpam_execute_error_tests(void) @return Consolidated status of all the tests run. **/ uint32_t -val_mpam_execute_membw_tests(void) +val_mpam_execute_membw_tests(uint32_t num_pe) { uint32_t status, i; @@ -126,13 +126,13 @@ val_mpam_execute_membw_tests(void) val_print_test_start("MEMORY BANDWIDTH"); g_curr_module = 1 << MEMORY_MODULE; - status = mem001_entry(); - status |= mem002_entry(); - status |= mem003_entry(); + status = mem001_entry(num_pe); + status |= mem002_entry(num_pe); + status |= mem003_entry(num_pe); - status |= monitor006_entry(); - status |= monitor007_entry(); - status |= monitor008_entry(); + status |= monitor006_entry(num_pe); + status |= monitor007_entry(num_pe); + status |= monitor008_entry(num_pe); val_print_test_end(status, "MEMORY BANDWIDTH"); @@ -148,7 +148,7 @@ val_mpam_execute_membw_tests(void) @return Consolidated status of all the tests run. **/ uint32_t -val_mpam_execute_register_tests(void) +val_mpam_execute_register_tests(uint32_t num_pe) { uint32_t status, i; @@ -171,12 +171,12 @@ val_mpam_execute_register_tests(void) val_print_test_start("REGISTER"); g_curr_module = 1 << REGISTER_MODULE; - status |= reg001_entry(); - status |= reg002_entry(); - status |= reg003_entry(); - status |= reg004_entry(); - status |= reg005_entry(); - status |= reg006_entry(); + status |= reg001_entry(num_pe); + status |= reg002_entry(num_pe); + status |= reg003_entry(num_pe); + status |= reg004_entry(num_pe); + status |= reg005_entry(num_pe); + status |= reg006_entry(num_pe); val_print_test_end(status, "REGISTER"); @@ -192,7 +192,7 @@ val_mpam_execute_register_tests(void) @return Consolidated status of all the tests run. **/ uint32_t -val_mpam_execute_cache_tests(void) +val_mpam_execute_cache_tests(uint32_t num_pe) { uint32_t status, i; @@ -215,20 +215,20 @@ val_mpam_execute_cache_tests(void) val_print_test_start("CACHE"); g_curr_module = 1 << CACHE_MODULE; - status |= partition001_entry(); - status |= partition002_entry(); - status |= partition003_entry(); - status |= partition004_entry(); - status |= partition005_entry(); - status |= partition006_entry(); + status |= partition001_entry(num_pe); + status |= partition002_entry(num_pe); + status |= partition003_entry(num_pe); + status |= partition004_entry(num_pe); + status |= partition005_entry(num_pe); + status |= partition006_entry(num_pe); - status |= feat001_entry(); + status |= feat001_entry(num_pe); - status |= monitor001_entry(); - status |= monitor002_entry(); - status |= monitor003_entry(); - status |= monitor004_entry(); - status |= monitor005_entry(); + status |= monitor001_entry(num_pe); + status |= monitor002_entry(num_pe); + status |= monitor003_entry(num_pe); + status |= monitor004_entry(num_pe); + status |= monitor005_entry(num_pe); val_print_test_end(status, "CACHE"); diff --git a/val/src/rule_based_orchestrator.c b/val/src/rule_based_orchestrator.c index 15dcf5dd..9ae0ea31 100644 --- a/val/src/rule_based_orchestrator.c +++ b/val/src/rule_based_orchestrator.c @@ -193,6 +193,7 @@ static uint32_t execute_rule_recursive(const acs_run_request_t *ctx, uint32_t precheck_status; uint32_t rule_support_status; uint32_t old_log_indent; + TEST_ENTRY_ID_e entry_id; RULE_ID_e child_rule_id; const RULE_ID_e *child_rule_list; @@ -240,11 +241,17 @@ static uint32_t execute_rule_recursive(const acs_run_request_t *ctx, } /* Execute any precheck required by the alias rule */ - if (rule_test_map[rule_id].test_entry_id != NULL_ENTRY) { + entry_id = rule_test_map[rule_id].test_entry_id; + if (entry_id != NULL_ENTRY) { + if ((entry_id >= TEST_ENTRY_SENTINEL) || + (test_entry_func_table[entry_id] == NULL)) { + val_print(ERROR, "\n Invalid alias precheck entry: 0x%x", entry_id); + rule_test_status = RESULT_FAIL(1); + goto exit_rule; + } old_log_indent = val_log_get_indent(); val_log_set_indent(indent); - precheck_status = - test_entry_func_table[rule_test_map[rule_id].test_entry_id](num_pe); + precheck_status = test_entry_func_table[entry_id](num_pe); val_log_set_indent(old_log_indent); if (GET_STATE(precheck_status) == TEST_FAIL) { @@ -303,11 +310,12 @@ static uint32_t execute_rule_recursive(const acs_run_request_t *ctx, print_alias_walk_banner(rule_id, indent, 0); } else if (rule_test_map[rule_id].flag == BASE_RULE) { - if (test_entry_func_table[rule_test_map[rule_id].test_entry_id] != NULL) { + entry_id = rule_test_map[rule_id].test_entry_id; + if ((entry_id != NULL_ENTRY) && (entry_id < TEST_ENTRY_SENTINEL) && + (test_entry_func_table[entry_id] != NULL)) { old_log_indent = val_log_get_indent(); val_log_set_indent(indent); - rule_test_status = - test_entry_func_table[rule_test_map[rule_id].test_entry_id](num_pe); + rule_test_status = test_entry_func_table[entry_id](num_pe); val_log_set_indent(old_log_indent); } else { val_print(ERROR, "\n\n Rule failed due to NULL entry \n\r ", 0); @@ -363,6 +371,7 @@ uint32_t filter_rule_list_by_cli(acs_run_request_t *ctx) const pcbsa_rule_entry_t *pcbsa_tbl = NULL; const vbsa_rule_entry_t *vbsa_tbl = NULL; const pfdi_rule_entry_t *pfdi_tbl = NULL; + const mpam_rule_entry_t *mpam_tbl = NULL; uint32_t tbl_count = 0; if (ctx == NULL) @@ -387,6 +396,9 @@ uint32_t filter_rule_list_by_cli(acs_run_request_t *ctx) } else if (ctx->arch_selection == ARCH_PFDI) { pfdi_tbl = pfdi_rule_list; add_count = pfdi_rule_list_len; + } else if (ctx->arch_selection == ARCH_SYS_MPAM) { + mpam_tbl = mpam_rule_list; + add_count = mpam_rule_list_len; } tbl_count = add_count; @@ -432,6 +444,12 @@ uint32_t filter_rule_list_by_cli(acs_run_request_t *ctx) if (!rule_in_list(rid, new_list, new_count)) new_list[new_count++] = rid; } + } else if (mpam_tbl) { + for (i = 0; i < add_count; i++) { + RULE_ID_e rid = mpam_tbl[i].rule_id; + if (!rule_in_list(rid, new_list, new_count)) + new_list[new_count++] = rid; + } } if (ctx->rule_list_owned && old_list != NULL) @@ -587,6 +605,20 @@ uint32_t filter_rule_list_by_cli(acs_run_request_t *ctx) break; } } + } else if (mpam_tbl) { + for (uint32_t ti = 0; ti < tbl_count; ti++) { + if (mpam_tbl[ti].rule_id == rule) { + found_entry = 1; + if (ctx->level_filter_mode == LVL_FILTER_ONLY) { + if ((uint32_t)mpam_tbl[ti].version != ctx->level_value) + skip = 1; + } else if (ctx->level_filter_mode == LVL_FILTER_MAX) { + if ((uint32_t)mpam_tbl[ti].version > ctx->level_value) + skip = 1; + } + break; + } + } } /* If not found in table, conservatively skip or keep? Keep by default */ diff --git a/val/src/rule_enum_string_map.c b/val/src/rule_enum_string_map.c index 88258001..07f993c7 100644 --- a/val/src/rule_enum_string_map.c +++ b/val/src/rule_enum_string_map.c @@ -275,6 +275,221 @@ char *rule_id_string[RULE_ID_SENTINEL] = { [S_L7MP_05] = "S_L7MP_05", [S_L7MP_08] = "S_L7MP_08", + /* SYS-MPAM */ + [BDJXQ] = "BDJXQ", + [DDGSM] = "DDGSM", + [RBCMK] = "RBCMK", + [CFXGZ] = "CFXGZ", + [FXVBB] = "FXVBB", + [LRZGD] = "LRZGD", + [PBSTK] = "PBSTK", + [KXMHB] = "KXMHB", + [CZHSY] = "CZHSY", + [RBWRS] = "RBWRS", + [QKQCF] = "QKQCF", + [CZSZX] = "CZSZX", + [NVNHD] = "NVNHD", + [SLJDR] = "SLJDR", + [VNVMD] = "VNVMD", + [SJFGX] = "SJFGX", + [YPHLH] = "YPHLH", + [RZCWR] = "RZCWR", + [MRWWK] = "MRWWK", + [XPPBS] = "XPPBS", + [CWTSC] = "CWTSC", + [JWKJD] = "JWKJD", + [SGBFN] = "SGBFN", + [ZTFBQ] = "ZTFBQ", + [JGWSM] = "JGWSM", + [LRNPR] = "LRNPR", + [VBHPB] = "VBHPB", + [WZXPM] = "WZXPM", + [CBBRW] = "CBBRW", + [CNQCS] = "CNQCS", + [BHHCR] = "BHHCR", + [BSLZQ] = "BSLZQ", + [WBZST] = "WBZST", + [YWPPT] = "YWPPT", + [BNKHP] = "BNKHP", + [KFDFD] = "KFDFD", + [XRQHH] = "XRQHH", + [VKQKB] = "VKQKB", + [TTSLQ] = "TTSLQ", + [RGSJV] = "RGSJV", + [MFRGP] = "MFRGP", + [CYKPC] = "CYKPC", + [KPNNZ] = "KPNNZ", + [JXRZM] = "JXRZM", + [RHYKB] = "RHYKB", + [LQQJN] = "LQQJN", + [KBJPW] = "KBJPW", + [YBYPZ] = "YBYPZ", + [CNGYT] = "CNGYT", + [HHQWY] = "HHQWY", + [WSXSL] = "WSXSL", + [YQBMW] = "YQBMW", + [YXZFG] = "YXZFG", + [DQNFB] = "DQNFB", + [YGZYL] = "YGZYL", + [PLZWM] = "PLZWM", + [DNNTB] = "DNNTB", + [LXXDB] = "LXXDB", + [MRZLG] = "MRZLG", + [NPVVN] = "NPVVN", + [HSFKH] = "HSFKH", + [XRHKL] = "XRHKL", + [GDMQZ] = "GDMQZ", + [MMXWZ] = "MMXWZ", + [QFCTM] = "QFCTM", + [CZMFT] = "CZMFT", + [XDZGT] = "XDZGT", + [HLHYS] = "HLHYS", + [GVCBB] = "GVCBB", + [KWGHQ] = "KWGHQ", + [TZWJG] = "TZWJG", + [VFJMZ] = "VFJMZ", + [WFQFS] = "WFQFS", + [GMCWW] = "GMCWW", + [CSLHH] = "CSLHH", + [QFRFQ] = "QFRFQ", + [RNSLZ] = "RNSLZ", + [NJXHP] = "NJXHP", + [XPPGG] = "XPPGG", + [ZVTKX] = "ZVTKX", + [RLHRV] = "RLHRV", + [ZRSRZ] = "ZRSRZ", + [WMPLL] = "WMPLL", + [LPLMM] = "LPLMM", + [BDRCM] = "BDRCM", + [ZHBXH] = "ZHBXH", + [SWNLN] = "SWNLN", + [VZBFH] = "VZBFH", + [CXZDR] = "CXZDR", + [FRTVY] = "FRTVY", + [DPZKC] = "DPZKC", + [DKYDB] = "DKYDB", + [GYMDB] = "GYMDB", + [CFHQL] = "CFHQL", + [HVRZS] = "HVRZS", + [WKZBJ] = "WKZBJ", + [BPRDL] = "BPRDL", + [WRXBV] = "WRXBV", + [NWVFK] = "NWVFK", + [PKRGZ] = "PKRGZ", + [VWHYW] = "VWHYW", + [PWSWQ] = "PWSWQ", + [XSYFH] = "XSYFH", + [ZQXQL] = "ZQXQL", + [CMZNL] = "CMZNL", + [PXSBS] = "PXSBS", + [ZDTLN] = "ZDTLN", + [ZFCRG] = "ZFCRG", + [TKBDC] = "TKBDC", + [MSPZM] = "MSPZM", + [JJKQP] = "JJKQP", + [NGDBL] = "NGDBL", + [MQRPH] = "MQRPH", + [RZDSR] = "RZDSR", + [MBNHC] = "MBNHC", + [JPLMZ] = "JPLMZ", + [DQTTD] = "DQTTD", + [RNWBS] = "RNWBS", + [GFYDF] = "GFYDF", + [WCQKV] = "WCQKV", + [ZGGMX] = "ZGGMX", + [TMCXJ] = "TMCXJ", + [YFMQP] = "YFMQP", + [DLSGF] = "DLSGF", + [WHJQG] = "WHJQG", + [VLSJS] = "VLSJS", + [RYRQJ] = "RYRQJ", + [QGXSZ] = "QGXSZ", + [VJDKF] = "VJDKF", + [DSCQB] = "DSCQB", + [FWCFZ] = "FWCFZ", + [PVNHR] = "PVNHR", + [KCWDZ] = "KCWDZ", + [XLWYW] = "XLWYW", + [GKWNB] = "GKWNB", + [LRTGP] = "LRTGP", + [NXKSF] = "NXKSF", + [FVFYC] = "FVFYC", + [ZTXDS] = "ZTXDS", + [VBZTW] = "VBZTW", + [FZHDC] = "FZHDC", + [YFVPY] = "YFVPY", + [NKTBN] = "NKTBN", + [NWKJR] = "NWKJR", + [SQSMV] = "SQSMV", + [WQJKV] = "WQJKV", + [XZXVK] = "XZXVK", + [NDMMK] = "NDMMK", + [VBBTL] = "VBBTL", + [XSTRM] = "XSTRM", + [JCNST] = "JCNST", + [DFWFP] = "DFWFP", + [GNQFY] = "GNQFY", + [MGGJW] = "MGGJW", + [HXNGD] = "HXNGD", + [RPGBQ] = "RPGBQ", + [MTGGZ] = "MTGGZ", + [DYNFP] = "DYNFP", + [WHSLQ] = "WHSLQ", + [GVBGS] = "GVBGS", + [QBKDG] = "QBKDG", + [DLSCZ] = "DLSCZ", + [ZWRQW] = "ZWRQW", + [VKKDP] = "VKKDP", + [XTQZR] = "XTQZR", + [XDCDL] = "XDCDL", + [JMLNM] = "JMLNM", + [XMLDN] = "XMLDN", + [VMTBP] = "VMTBP", + [WXKWK] = "WXKWK", + [MGXDK] = "MGXDK", + [HJRZC] = "HJRZC", + [SQTSJ] = "SQTSJ", + [VZWYW] = "VZWYW", + [PNPQQ] = "PNPQQ", + [SJFMB] = "SJFMB", + [VYLZC] = "VYLZC", + [QBQJG] = "QBQJG", + [PFNBV] = "PFNBV", + [CZZZK] = "CZZZK", + [HVNKJ] = "HVNKJ", + [TMMMD] = "TMMMD", + [QDSPY] = "QDSPY", + [PPJSM] = "PPJSM", + [GLPPK] = "GLPPK", + [NRGQD] = "NRGQD", + [KVGWS] = "KVGWS", + [KVHTZ] = "KVHTZ", + [ZRDMM] = "ZRDMM", + [YLCVK] = "YLCVK", + [YJCDR] = "YJCDR", + [YVSNK] = "YVSNK", + [JLYJJ] = "JLYJJ", + [MBDJF] = "MBDJF", + [LVCGQ] = "LVCGQ", + [DMKKT] = "DMKKT", + [VTFQK] = "VTFQK", + [CTGKD] = "CTGKD", + [RDMVJ] = "RDMVJ", + [KNNBY] = "KNNBY", + [ZPWLC] = "ZPWLC", + [DYDFT] = "DYDFT", + [HXLMF] = "HXLMF", + [QCYPH] = "QCYPH", + [FLWNK] = "FLWNK", + [GTKCX] = "GTKCX", + [DFBBW] = "DFBBW", + [FYTQL] = "FYTQL", + [KZBWG] = "KZBWG", + [YCBKB] = "YCBKB", + [TVYHS] = "TVYHS", + [RJFKG] = "RJFKG", + [FKNKB] = "FKNKB", + /* ETE */ [ETE_01] = "ETE_01", [ETE_02] = "ETE_02", @@ -582,6 +797,10 @@ char *module_name_string[MODULE_ID_SENTINEL] = { [NIST] = "NIST", [PCIE] = "PCIE", [MPAM] = "MPAM", + [MPAM_CACHE] = "CACHE", + [MPAM_REG] = "REG", + [MPAM_ERROR] = "ERROR", + [MPAM_MBWU] = "MBWU", [ETE] = "ETE", [TPM] = "TPM", [POWER_WAKEUP] = "POWER_WAKEUP", diff --git a/val/src/rule_lookup.c b/val/src/rule_lookup.c index 86c0cf60..81362032 100644 --- a/val/src/rule_lookup.c +++ b/val/src/rule_lookup.c @@ -407,6 +407,224 @@ const vbsa_rule_entry_t vbsa_rule_list[] = { { RULE_ID_SENTINEL, VBSA_LEVEL_SENTINEL } }; +/* SYS-MPAM rule checklist based on the MPAM system architecture */ +const mpam_rule_entry_t mpam_rule_list[] = { + { BDJXQ, MPAM_VERSION_B_c }, + { DDGSM, MPAM_VERSION_B_c }, + { RBCMK, MPAM_VERSION_B_c }, + { CFXGZ, MPAM_VERSION_B_c }, + { FXVBB, MPAM_VERSION_B_c }, + { LRZGD, MPAM_VERSION_B_c }, + { PBSTK, MPAM_VERSION_B_c }, + { KXMHB, MPAM_VERSION_B_c }, + { CZHSY, MPAM_VERSION_B_c }, + { RBWRS, MPAM_VERSION_B_c }, + { QKQCF, MPAM_VERSION_B_c }, + { CZSZX, MPAM_VERSION_B_c }, + { NVNHD, MPAM_VERSION_B_c }, + { SLJDR, MPAM_VERSION_B_c }, + { VNVMD, MPAM_VERSION_B_c }, + { SJFGX, MPAM_VERSION_B_c }, + { YPHLH, MPAM_VERSION_B_c }, + { RZCWR, MPAM_VERSION_B_c }, + { MRWWK, MPAM_VERSION_B_c }, + { XPPBS, MPAM_VERSION_B_c }, + { CWTSC, MPAM_VERSION_B_c }, + { JWKJD, MPAM_VERSION_B_c }, + { SGBFN, MPAM_VERSION_B_c }, + { ZTFBQ, MPAM_VERSION_B_c }, + { JGWSM, MPAM_VERSION_B_c }, + { LRNPR, MPAM_VERSION_B_c }, + { VBHPB, MPAM_VERSION_B_c }, + { WZXPM, MPAM_VERSION_B_c }, + { CBBRW, MPAM_VERSION_B_c }, + { CNQCS, MPAM_VERSION_B_c }, + { BHHCR, MPAM_VERSION_B_c }, + { BSLZQ, MPAM_VERSION_B_c }, + { WBZST, MPAM_VERSION_B_c }, + { YWPPT, MPAM_VERSION_B_c }, + { BNKHP, MPAM_VERSION_B_c }, + { KFDFD, MPAM_VERSION_B_c }, + { XRQHH, MPAM_VERSION_B_c }, + { VKQKB, MPAM_VERSION_B_c }, + { TTSLQ, MPAM_VERSION_B_c }, + { RGSJV, MPAM_VERSION_B_c }, + { MFRGP, MPAM_VERSION_B_c }, + { CYKPC, MPAM_VERSION_B_c }, + { KPNNZ, MPAM_VERSION_B_c }, + { JXRZM, MPAM_VERSION_B_c }, + { RHYKB, MPAM_VERSION_B_c }, + { LQQJN, MPAM_VERSION_B_c }, + { KBJPW, MPAM_VERSION_B_c }, + { YBYPZ, MPAM_VERSION_B_c }, + { CNGYT, MPAM_VERSION_B_c }, + { HHQWY, MPAM_VERSION_B_c }, + { WSXSL, MPAM_VERSION_B_c }, + { YQBMW, MPAM_VERSION_B_c }, + { YXZFG, MPAM_VERSION_B_c }, + { DQNFB, MPAM_VERSION_B_c }, + { YGZYL, MPAM_VERSION_B_c }, + { PLZWM, MPAM_VERSION_B_c }, + { DNNTB, MPAM_VERSION_B_c }, + { LXXDB, MPAM_VERSION_B_c }, + { MRZLG, MPAM_VERSION_B_c }, + { NPVVN, MPAM_VERSION_B_c }, + { HSFKH, MPAM_VERSION_B_c }, + { XRHKL, MPAM_VERSION_B_c }, + { GDMQZ, MPAM_VERSION_B_c }, + { MMXWZ, MPAM_VERSION_B_c }, + { QFCTM, MPAM_VERSION_B_c }, + { CZMFT, MPAM_VERSION_B_c }, + { XDZGT, MPAM_VERSION_B_c }, + { HLHYS, MPAM_VERSION_B_c }, + { GVCBB, MPAM_VERSION_B_c }, + { KWGHQ, MPAM_VERSION_B_c }, + { TZWJG, MPAM_VERSION_B_c }, + { VFJMZ, MPAM_VERSION_B_c }, + { WFQFS, MPAM_VERSION_B_c }, + { GMCWW, MPAM_VERSION_B_c }, + { CSLHH, MPAM_VERSION_B_c }, + { QFRFQ, MPAM_VERSION_B_c }, + { RNSLZ, MPAM_VERSION_B_c }, + { NJXHP, MPAM_VERSION_B_c }, + { XPPGG, MPAM_VERSION_B_c }, + { ZVTKX, MPAM_VERSION_B_c }, + { RLHRV, MPAM_VERSION_B_c }, + { ZRSRZ, MPAM_VERSION_B_c }, + { WMPLL, MPAM_VERSION_B_c }, + { LPLMM, MPAM_VERSION_B_c }, + { BDRCM, MPAM_VERSION_B_c }, + { ZHBXH, MPAM_VERSION_B_c }, + { SWNLN, MPAM_VERSION_B_c }, + { VZBFH, MPAM_VERSION_B_c }, + { CXZDR, MPAM_VERSION_B_c }, + { FRTVY, MPAM_VERSION_B_c }, + { DPZKC, MPAM_VERSION_B_c }, + { DKYDB, MPAM_VERSION_B_c }, + { GYMDB, MPAM_VERSION_B_c }, + { CFHQL, MPAM_VERSION_B_c }, + { HVRZS, MPAM_VERSION_B_c }, + { WKZBJ, MPAM_VERSION_B_c }, + { BPRDL, MPAM_VERSION_B_c }, + { WRXBV, MPAM_VERSION_B_c }, + { NWVFK, MPAM_VERSION_B_c }, + { PKRGZ, MPAM_VERSION_B_c }, + { VWHYW, MPAM_VERSION_B_c }, + { PWSWQ, MPAM_VERSION_B_c }, + { XSYFH, MPAM_VERSION_B_c }, + { ZQXQL, MPAM_VERSION_B_c }, + { CMZNL, MPAM_VERSION_B_c }, + { PXSBS, MPAM_VERSION_B_c }, + { ZDTLN, MPAM_VERSION_B_c }, + { ZFCRG, MPAM_VERSION_B_c }, + { TKBDC, MPAM_VERSION_B_c }, + { MSPZM, MPAM_VERSION_B_c }, + { JJKQP, MPAM_VERSION_B_c }, + { NGDBL, MPAM_VERSION_B_c }, + { MQRPH, MPAM_VERSION_B_c }, + { RZDSR, MPAM_VERSION_B_c }, + { MBNHC, MPAM_VERSION_B_c }, + { JPLMZ, MPAM_VERSION_B_c }, + { DQTTD, MPAM_VERSION_B_c }, + { RNWBS, MPAM_VERSION_B_c }, + { GFYDF, MPAM_VERSION_B_c }, + { WCQKV, MPAM_VERSION_B_c }, + { ZGGMX, MPAM_VERSION_B_c }, + { TMCXJ, MPAM_VERSION_B_c }, + { YFMQP, MPAM_VERSION_B_c }, + { DLSGF, MPAM_VERSION_B_c }, + { WHJQG, MPAM_VERSION_B_c }, + { VLSJS, MPAM_VERSION_B_c }, + { RYRQJ, MPAM_VERSION_B_c }, + { QGXSZ, MPAM_VERSION_B_c }, + { VJDKF, MPAM_VERSION_B_c }, + { DSCQB, MPAM_VERSION_B_c }, + { FWCFZ, MPAM_VERSION_B_c }, + { PVNHR, MPAM_VERSION_B_c }, + { KCWDZ, MPAM_VERSION_B_c }, + { XLWYW, MPAM_VERSION_B_c }, + { GKWNB, MPAM_VERSION_B_c }, + { LRTGP, MPAM_VERSION_B_c }, + { NXKSF, MPAM_VERSION_B_c }, + { FVFYC, MPAM_VERSION_B_c }, + { ZTXDS, MPAM_VERSION_B_c }, + { VBZTW, MPAM_VERSION_B_c }, + { FZHDC, MPAM_VERSION_B_c }, + { YFVPY, MPAM_VERSION_B_c }, + { NKTBN, MPAM_VERSION_B_c }, + { NWKJR, MPAM_VERSION_B_c }, + { SQSMV, MPAM_VERSION_B_c }, + { WQJKV, MPAM_VERSION_B_c }, + { XZXVK, MPAM_VERSION_B_c }, + { NDMMK, MPAM_VERSION_B_c }, + { VBBTL, MPAM_VERSION_B_c }, + { XSTRM, MPAM_VERSION_B_c }, + { JCNST, MPAM_VERSION_B_c }, + { DFWFP, MPAM_VERSION_B_c }, + { GNQFY, MPAM_VERSION_B_c }, + { MGGJW, MPAM_VERSION_B_c }, + { HXNGD, MPAM_VERSION_B_c }, + { RPGBQ, MPAM_VERSION_B_c }, + { MTGGZ, MPAM_VERSION_B_c }, + { DYNFP, MPAM_VERSION_B_c }, + { WHSLQ, MPAM_VERSION_B_c }, + { GVBGS, MPAM_VERSION_B_c }, + { QBKDG, MPAM_VERSION_B_c }, + { DLSCZ, MPAM_VERSION_B_c }, + { ZWRQW, MPAM_VERSION_B_c }, + { VKKDP, MPAM_VERSION_B_c }, + { XTQZR, MPAM_VERSION_B_c }, + { XDCDL, MPAM_VERSION_B_c }, + { JMLNM, MPAM_VERSION_B_c }, + { XMLDN, MPAM_VERSION_B_c }, + { VMTBP, MPAM_VERSION_B_c }, + { WXKWK, MPAM_VERSION_B_c }, + { MGXDK, MPAM_VERSION_B_c }, + { HJRZC, MPAM_VERSION_B_c }, + { SQTSJ, MPAM_VERSION_B_c }, + { VZWYW, MPAM_VERSION_B_c }, + { PNPQQ, MPAM_VERSION_B_c }, + { SJFMB, MPAM_VERSION_B_c }, + { VYLZC, MPAM_VERSION_B_c }, + { QBQJG, MPAM_VERSION_B_c }, + { PFNBV, MPAM_VERSION_B_c }, + { CZZZK, MPAM_VERSION_B_c }, + { HVNKJ, MPAM_VERSION_B_c }, + { TMMMD, MPAM_VERSION_B_c }, + { QDSPY, MPAM_VERSION_B_c }, + { PPJSM, MPAM_VERSION_B_c }, + { GLPPK, MPAM_VERSION_B_c }, + { NRGQD, MPAM_VERSION_B_c }, + { KVGWS, MPAM_VERSION_B_c }, + { KVHTZ, MPAM_VERSION_B_c }, + { ZRDMM, MPAM_VERSION_B_c }, + { YLCVK, MPAM_VERSION_B_c }, + { YJCDR, MPAM_VERSION_B_c }, + { YVSNK, MPAM_VERSION_B_c }, + { JLYJJ, MPAM_VERSION_B_c }, + { MBDJF, MPAM_VERSION_B_c }, + { LVCGQ, MPAM_VERSION_B_c }, + { DMKKT, MPAM_VERSION_B_c }, + { VTFQK, MPAM_VERSION_B_c }, + { CTGKD, MPAM_VERSION_B_c }, + { RDMVJ, MPAM_VERSION_B_c }, + { KNNBY, MPAM_VERSION_B_c }, + { ZPWLC, MPAM_VERSION_B_c }, + { DYDFT, MPAM_VERSION_B_c }, + { HXLMF, MPAM_VERSION_B_c }, + { QCYPH, MPAM_VERSION_B_c }, + { FLWNK, MPAM_VERSION_B_c }, + { GTKCX, MPAM_VERSION_B_c }, + { DFBBW, MPAM_VERSION_B_c }, + { FYTQL, MPAM_VERSION_B_c }, + { KZBWG, MPAM_VERSION_B_c }, + { YCBKB, MPAM_VERSION_B_c }, + { TVYHS, MPAM_VERSION_B_c }, + { RJFKG, MPAM_VERSION_B_c }, + { FKNKB, MPAM_VERSION_B_c }, + { RULE_ID_SENTINEL, MPAM_VERSION_SENTINEL } +}; + /* PFDI rule checklist (single level at present) */ const pfdi_rule_entry_t pfdi_rule_list[] = { { R0040, PFDI_LEVEL_1 }, @@ -449,3 +667,4 @@ const uint32_t sbsa_rule_list_len = (sizeof(sbsa_rule_list) / sizeof(sbsa_rule const uint32_t bsa_rule_list_len = (sizeof(bsa_rule_list) / sizeof(bsa_rule_list[0])) - 1U; const uint32_t vbsa_rule_list_len = (sizeof(vbsa_rule_list) / sizeof(vbsa_rule_list[0])) - 1U; const uint32_t pfdi_rule_list_len = (sizeof(pfdi_rule_list) / sizeof(pfdi_rule_list[0])) - 1U; +const uint32_t mpam_rule_list_len = (sizeof(mpam_rule_list) / sizeof(mpam_rule_list[0])) - 1U; diff --git a/val/src/rule_metadata.c b/val/src/rule_metadata.c index f714bfda..ed5695c6 100644 --- a/val/src/rule_metadata.c +++ b/val/src/rule_metadata.c @@ -2265,7 +2265,769 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = { .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI | PLATFORM_LINUX, .flag = ALIAS_RULE, }, - /* MPAM */ + /* SYS-MPAM */ + [BDJXQ] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check request PARTID and PMG monitor labeling", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [CFXGZ] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [FXVBB] = { + .test_entry_id = REG004_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM for RME Feature Test", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 4), + }, + [KXMHB] = { + .test_entry_id = REG004_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM for RME Feature Test", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 4), + }, + [XPPBS] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [CWTSC] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [ZTFBQ] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [JGWSM] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [LRNPR] = { + .test_entry_id = REG005_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MSC Four-Space Region Test", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 5), + }, + [VBHPB] = { + .test_entry_id = REG004_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM for RME Feature Test", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 4), + }, + [WZXPM] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [JXRZM] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PMG Storage by CPOR Nodes", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [RHYKB] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PMG Storage by CPOR Nodes", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [CNGYT] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [HHQWY] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [WSXSL] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [YQBMW] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [YXZFG] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [DQNFB] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [PLZWM] = { + .test_entry_id = ERROR009_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check RIS no control error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 9, + }, + [DNNTB] = { + .test_entry_id = ERROR010_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MSMON_CFG_MON_SEL Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 10, + }, + [LXXDB] = { + .test_entry_id = ERROR010_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MSMON_CFG_MON_SEL Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 10, + }, + [MRZLG] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [NPVVN] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [HSFKH] = { + .test_entry_id = ERROR012_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MPAM IDR Zero for Undefined RIS", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 15, + }, + [GDMQZ] = { + .test_entry_id = REG005_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MSC Four-Space Region Test", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 5), + }, + [MMXWZ] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [GVCBB] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [KWGHQ] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [TZWJG] = { + .test_entry_id = FEAT001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PARTID enable status is global to the MSC", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 25, + }, + [VFJMZ] = { + .test_entry_id = FEAT001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check resource allocation for disabled PARTID", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 25, + }, + [RNSLZ] = { + .test_entry_id = REG006_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check NFU bit when PARTID NRW is impl", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_REGISTER_TEST_NUM_BASE + 6), + }, + [XPPGG] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [ZVTKX] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [RLHRV] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [ZRSRZ] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [WMPLL] = { + .test_entry_id = PARTITION001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CPOR Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 1, + }, + [BDRCM] = { + .test_entry_id = PARTITION004_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CASSOC Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 4, + }, + [ZHBXH] = { + .test_entry_id = PARTITION002_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CCAP Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 2, + }, + [SWNLN] = { + .test_entry_id = PARTITION005_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMAX Partitioning with softlimit", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 5, + }, + [VZBFH] = { + .test_entry_id = PARTITION005_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMAX Partitioning with softlimit", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 5, + }, + [CXZDR] = { + .test_entry_id = PARTITION006_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMIN resource controls", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 6, + }, + [FRTVY] = { + .test_entry_id = PARTITION006_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMIN resource controls", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 6, + }, + [DPZKC] = { + .test_entry_id = PARTITION006_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMIN resource controls", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 6, + }, + [DKYDB] = { + .test_entry_id = MEM001_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWPBM Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 1, + }, + [GYMDB] = { + .test_entry_id = MEM001_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWPBM Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 1, + }, + [CFHQL] = { + .test_entry_id = MEM001_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWPBM Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 1, + }, + [WKZBJ] = { + .test_entry_id = MEM002_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWMIN Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 2, + }, + [WRXBV] = { + .test_entry_id = MEM002_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWMIN Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 2, + }, + [NWVFK] = { + .test_entry_id = MEM003_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWMAX Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 3, + }, + [VWHYW] = { + .test_entry_id = MEM003_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWMAX Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 3, + }, + [ZGGMX] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PMG Storage by CPOR Nodes", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [YFMQP] = { + .test_entry_id = MEM001_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWPBM Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 1, + }, + [WHJQG] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [RYRQJ] = { + .test_entry_id = INTR004_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MBWU_L overflow interrupt status", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 18, + }, + [VJDKF] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PMG Storage by CPOR Nodes", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [DSCQB] = { + .test_entry_id = MONITOR005_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check MSMON CTL Disable Behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 5, + }, + [FWCFZ] = { + .test_entry_id = MONITOR008_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU MSMON OFLOW Reset behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 6, + }, + [PVNHR] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [GKWNB] = { + .test_entry_id = MONITOR001_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check PMG Storage by CPOR Nodes", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 1, + }, + [NXKSF] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [VBZTW] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [WQJKV] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [XZXVK] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [NDMMK] = { + .test_entry_id = MONITOR008_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU MSMON OFLOW Reset behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 6, + }, + [VBBTL] = { + .test_entry_id = MONITOR005_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check MSMON CTL Disable Behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MONITOR_TEST_NUM_BASE + 5, + }, + [XSTRM] = { + .test_entry_id = MONITOR007_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU OFLOW_FRZ overflow behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 5, + }, + [GNQFY] = { + .test_entry_id = MONITOR008_ENTRY, + .module_id = MPAM_MBWU, + .rule_desc = "Check MBWU MSMON OFLOW Reset behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_MEMORY_TEST_NUM_BASE + 6, + }, + [DYNFP] = { + .test_entry_id = ERROR014_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MPAM error overwrite behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_ERROR_TEST_NUM_BASE + 17), + }, + [WHSLQ] = { + .test_entry_id = ERROR001_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC PARTID selection range error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 1, + }, + [GVBGS] = { + .test_entry_id = ERROR014_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MPAM error overwrite behavior", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = (ACS_MPAM_ERROR_TEST_NUM_BASE + 17), + }, + [QBKDG] = { + .test_entry_id = ERROR013_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MPAMF_ESR.RIS field correctness", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 16, + }, + [DLSCZ] = { + .test_entry_id = ERROR001_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC PARTID selection range error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 1, + }, + [ZWRQW] = { + .test_entry_id = ERROR003_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSMON ConfigID out-of-range Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 3, + }, + [VKKDP] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [XTQZR] = { + .test_entry_id = ERROR012_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MPAM IDR Zero for Undefined RIS", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 15, + }, + [XDCDL] = { + .test_entry_id = ERROR008_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MPAMCFG_PART_SEL error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 8, + }, + [VMTBP] = { + .test_entry_id = ERROR005_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC MONITOR selection range Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 5, + }, + [HJRZC] = { + .test_entry_id = ERROR010_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MSMON_CFG_MON_SEL Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 10, + }, + [SQTSJ] = { + .test_entry_id = ERROR010_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Undef RIS MSMON_CFG_MON_SEL Err", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 10, + }, + [PNPQQ] = { + .test_entry_id = ERROR001_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC PARTID selection range error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 1, + }, + [PFNBV] = { + .test_entry_id = ERROR001_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC PARTID selection range error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 1, + }, + [CZZZK] = { + .test_entry_id = ERROR007_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Unexpected internal error", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 7, + }, + [GLPPK] = { + .test_entry_id = INTR001_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check Level-Sensitive Error Interrupt", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 12, + }, + [KVGWS] = { + .test_entry_id = INTR002_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MSC Edge-Trigger Error Interrupt", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 13, + }, + [YLCVK] = { + .test_entry_id = INTR003_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MBWU Mon Overflow interrupt", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 14, + }, + [YJCDR] = { + .test_entry_id = INTR005_ENTRY, + .module_id = MPAM_ERROR, + .rule_desc = "Check MBWU Oflow MSI interrupt status", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_ERROR_TEST_NUM_BASE + 19, + }, + [JLYJJ] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [KNNBY] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [ZPWLC] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [DYDFT] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [GTKCX] = { + .test_entry_id = REG001_ENTRY, + .module_id = MPAM_REG, + .rule_desc = "Check MPAM Version EXT Bit Check", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_REGISTER_TEST_NUM_BASE + 1, + }, + [YCBKB] = { + .test_entry_id = PARTITION004_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CASSOC Partitioning", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 4, + }, + [RJFKG] = { + .test_entry_id = PARTITION005_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMAX Partitioning with softlimit", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 5, + }, + [FKNKB] = { + .test_entry_id = PARTITION006_ENTRY, + .module_id = MPAM_CACHE, + .rule_desc = "Check CMIN resource controls", + .platform_bitmask = PLATFORM_UEFI | PLATFORM_BAREMETAL, + .flag = BASE_RULE, + .test_num = ACS_MPAM_CACHE_TEST_NUM_BASE + 6, + }, + + /* SBSA MPAM */ [S_L7MP_01] = { .test_entry_id = MPAM001_ENTRY, .module_id = MPAM, @@ -3508,7 +4270,74 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { /* TARGET_UEFI */ #if defined(TARGET_UEFI) -#ifndef PFDI_DT_BUILD +#if defined(PFDI_DT_BUILD) + [PFDI001_ENTRY] = pfdi001_entry, + [PFDI002_ENTRY] = pfdi002_entry, + [PFDI003_ENTRY] = pfdi003_entry, + [PFDI004_ENTRY] = pfdi004_entry, + [PFDI005_ENTRY] = pfdi005_entry, + [PFDI006_ENTRY] = pfdi006_entry, + [PFDI007_ENTRY] = pfdi007_entry, + [PFDI008_ENTRY] = pfdi008_entry, + [PFDI009_ENTRY] = pfdi009_entry, + [PFDI010_ENTRY] = pfdi010_entry, + [PFDI011_ENTRY] = pfdi011_entry, + [PFDI012_ENTRY] = pfdi012_entry, + [PFDI013_ENTRY] = pfdi013_entry, + [PFDI014_ENTRY] = pfdi014_entry, + [PFDI015_ENTRY] = pfdi015_entry, + [PFDI016_ENTRY] = pfdi016_entry, + [PFDI017_ENTRY] = pfdi017_entry, + [PFDI018_ENTRY] = pfdi018_entry, + [PFDI019_ENTRY] = pfdi019_entry, + [PFDI020_ENTRY] = pfdi020_entry, + [PFDI021_ENTRY] = pfdi021_entry, + [PFDI022_ENTRY] = pfdi022_entry, + [PFDI023_ENTRY] = pfdi023_entry, + [PFDI024_ENTRY] = pfdi024_entry, + [PFDI025_ENTRY] = pfdi025_entry, + [PFDI026_ENTRY] = pfdi026_entry, + [PFDI027_ENTRY] = pfdi027_entry, + [PFDI028_ENTRY] = pfdi028_entry, + [PFDI029_ENTRY] = pfdi029_entry, + [PFDI030_ENTRY] = pfdi030_entry, + [PFDI031_ENTRY] = pfdi031_entry, +#elif defined(SYS_MPAM_UEFI_BUILD) + [FEAT001_ENTRY] = feat001_entry, + [REG001_ENTRY] = reg001_entry, + [REG004_ENTRY] = reg004_entry, + [PARTITION001_ENTRY] = partition001_entry, + [REG005_ENTRY] = reg005_entry, + [MONITOR001_ENTRY] = monitor001_entry, + [ERROR008_ENTRY] = error008_entry, + [ERROR009_ENTRY] = error009_entry, + [ERROR010_ENTRY] = error010_entry, + [ERROR011_ENTRY] = error011_entry, + [ERROR012_ENTRY] = error012_entry, + [MEM001_ENTRY] = mem001_entry, + [REG006_ENTRY] = reg006_entry, + [PARTITION004_ENTRY] = partition004_entry, + [PARTITION002_ENTRY] = partition002_entry, + [PARTITION005_ENTRY] = partition005_entry, + [PARTITION006_ENTRY] = partition006_entry, + [MEM002_ENTRY] = mem002_entry, + [MEM003_ENTRY] = mem003_entry, + [MONITOR007_ENTRY] = monitor007_entry, + [INTR004_ENTRY] = intr004_entry, + [MONITOR005_ENTRY] = monitor005_entry, + [MONITOR008_ENTRY] = monitor008_entry, + [MONITOR006_ENTRY] = monitor006_entry, + [ERROR014_ENTRY] = error014_entry, + [ERROR001_ENTRY] = error001_entry, + [ERROR003_ENTRY] = error003_entry, + [ERROR005_ENTRY] = error005_entry, + [ERROR013_ENTRY] = error013_entry, + [ERROR007_ENTRY] = error007_entry, + [INTR001_ENTRY] = intr001_entry, + [INTR002_ENTRY] = intr002_entry, + [INTR003_ENTRY] = intr003_entry, + [INTR005_ENTRY] = intr005_entry, +#else [D001_ENTRY] = d001_entry, [D002_ENTRY] = d002_entry, [D003_ENTRY] = d003_entry, @@ -3889,44 +4718,47 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [W003_ENTRY] = w003_entry, [V_L1WK_02_05_ENTRY] = v_l1wk_02_05_entry, [V_L1PP_00_ENTRY] = v_l1pp_00_entry, -#endif /* PFDI_DT_BUILD */ -#if defined(PFDI_DT_BUILD) - [PFDI001_ENTRY] = pfdi001_entry, - [PFDI002_ENTRY] = pfdi002_entry, - [PFDI003_ENTRY] = pfdi003_entry, - [PFDI004_ENTRY] = pfdi004_entry, - [PFDI005_ENTRY] = pfdi005_entry, - [PFDI006_ENTRY] = pfdi006_entry, - [PFDI007_ENTRY] = pfdi007_entry, - [PFDI008_ENTRY] = pfdi008_entry, - [PFDI009_ENTRY] = pfdi009_entry, - [PFDI010_ENTRY] = pfdi010_entry, - [PFDI011_ENTRY] = pfdi011_entry, - [PFDI012_ENTRY] = pfdi012_entry, - [PFDI013_ENTRY] = pfdi013_entry, - [PFDI014_ENTRY] = pfdi014_entry, - [PFDI015_ENTRY] = pfdi015_entry, - [PFDI016_ENTRY] = pfdi016_entry, - [PFDI017_ENTRY] = pfdi017_entry, - [PFDI018_ENTRY] = pfdi018_entry, - [PFDI019_ENTRY] = pfdi019_entry, - [PFDI020_ENTRY] = pfdi020_entry, - [PFDI021_ENTRY] = pfdi021_entry, - [PFDI022_ENTRY] = pfdi022_entry, - [PFDI023_ENTRY] = pfdi023_entry, - [PFDI024_ENTRY] = pfdi024_entry, - [PFDI025_ENTRY] = pfdi025_entry, - [PFDI026_ENTRY] = pfdi026_entry, - [PFDI027_ENTRY] = pfdi027_entry, - [PFDI028_ENTRY] = pfdi028_entry, - [PFDI029_ENTRY] = pfdi029_entry, - [PFDI030_ENTRY] = pfdi030_entry, - [PFDI031_ENTRY] = pfdi031_entry, -#endif /* PFDI_DT_BUILD */ +#endif /* UEFI build variant */ #endif /* TARGET_UEFI */ /* TARGET_BAREMETAL */ #if defined(TARGET_BAREMETAL) +#if defined(BAREMETAL_MPAM_BUILD) + [FEAT001_ENTRY] = feat001_entry, + [REG001_ENTRY] = reg001_entry, + [REG004_ENTRY] = reg004_entry, + [PARTITION001_ENTRY] = partition001_entry, + [REG005_ENTRY] = reg005_entry, + [MONITOR001_ENTRY] = monitor001_entry, + [ERROR008_ENTRY] = error008_entry, + [ERROR009_ENTRY] = error009_entry, + [ERROR010_ENTRY] = error010_entry, + [ERROR011_ENTRY] = error011_entry, + [ERROR012_ENTRY] = error012_entry, + [MEM001_ENTRY] = mem001_entry, + [REG006_ENTRY] = reg006_entry, + [PARTITION004_ENTRY] = partition004_entry, + [PARTITION002_ENTRY] = partition002_entry, + [PARTITION005_ENTRY] = partition005_entry, + [PARTITION006_ENTRY] = partition006_entry, + [MEM002_ENTRY] = mem002_entry, + [MEM003_ENTRY] = mem003_entry, + [MONITOR007_ENTRY] = monitor007_entry, + [INTR004_ENTRY] = intr004_entry, + [MONITOR005_ENTRY] = monitor005_entry, + [MONITOR008_ENTRY] = monitor008_entry, + [MONITOR006_ENTRY] = monitor006_entry, + [ERROR014_ENTRY] = error014_entry, + [ERROR001_ENTRY] = error001_entry, + [ERROR003_ENTRY] = error003_entry, + [ERROR005_ENTRY] = error005_entry, + [ERROR013_ENTRY] = error013_entry, + [ERROR007_ENTRY] = error007_entry, + [INTR001_ENTRY] = intr001_entry, + [INTR002_ENTRY] = intr002_entry, + [INTR003_ENTRY] = intr003_entry, + [INTR005_ENTRY] = intr005_entry, +#else #if defined(BAREMETAL_PCBSA_BUILD) /* PC_BSA Baremetal build to selected test entries only */ [PE001_ENTRY] = pe001_entry, @@ -4489,6 +5321,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [PCI_MM_07_ENTRY] = pci_mm_07_entry, [PCI_MM_05_ENTRY] = pci_mm_05_entry, #endif /* TARGET_PC_BAREMETAL */ +#endif /* BAREMETAL_MPAM_BUILD */ #endif /* TARGET_BAREMETAL */ }; diff --git a/val/val.cmake b/val/val.cmake index 29257a10..b0bea0da 100644 --- a/val/val.cmake +++ b/val/val.cmake @@ -132,16 +132,11 @@ function(acs_add_val_library_for_acs ACS_NAME) "${ROOT_DIR}/val/src/pc_bsa_execute_test.c" "${ROOT_DIR}/val/src/bsa_execute_test.c" "${ROOT_DIR}/val/src/sbsa_execute_test.c" - "${ROOT_DIR}/val/src/rule_based_execution_helpers.c" - "${ROOT_DIR}/val/src/rule_based_orchestrator.c" - "${ROOT_DIR}/val/src/rule_enum_string_map.c" - "${ROOT_DIR}/val/src/rule_lookup.c" - "${ROOT_DIR}/val/src/rule_metadata.c" + "${ROOT_DIR}/val/src/mpam_execute_test.c" "${ROOT_DIR}/val/src/acs_exerciser.c" - "${ROOT_DIR}/val/src/rule_based_execution_enum.h" ) list(APPEND remove_sources ${common_remove_sources}) - list(APPEND extra_defs BAREMETAL_MPAM_BUILD) + list(APPEND extra_defs BAREMETAL_MPAM_BUILD COMPILE_RB_EXE) else() message(FATAL_ERROR "Unsupported ACS value for val library: ${ACS_NAME}") endif()