diff --git a/val/include/acs_pcie_spec.h b/val/include/acs_pcie_spec.h
index c8592ae7..bcd82620 100644
--- a/val/include/acs_pcie_spec.h
+++ b/val/include/acs_pcie_spec.h
@@ -156,6 +156,7 @@
 #define TYPE1_P_MEM_LU  0x2C    /* Prefetchable Limit Upper Offset */
 
 /* Type 1 Bridge Control Register */
+#define BRIDGE_CTRL_SERRE_SET   (1U << 17)
 #define BRIDGE_CTRL_SBR_SET     0x400000
 
 /* Memory Base Reg Shifts */
diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c
index 262bdf4e..2bb6a280 100644
--- a/val/src/acs_pcie.c
+++ b/val/src/acs_pcie.c
@@ -1267,6 +1267,13 @@ val_pcie_enable_eru(uint32_t bdf)
   dis_mask = (1 << CR_SERRE_SHIFT);
   val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | dis_mask);
 
+  /* Enable SERR# forwarding for functions with a Type 1 configuration header. */
+  if (val_pcie_function_header_type(bdf) == TYPE1_HEADER)
+  {
+      val_pcie_read_cfg(bdf, TYPE01_ILR, &reg_value);
+      val_pcie_write_cfg(bdf, TYPE01_ILR, reg_value | BRIDGE_CTRL_SERRE_SET);
+  }
+
   /* Get the PCI Express Capability structure offset and
    * use that offset to read the Device Control register
    */