From 42403b0b0c8760ef1fd08beae9eb2d0068b63556 Mon Sep 17 00:00:00 2001 From: Sahil Shakil Malpekar Date: Mon, 5 Oct 2026 16:25:05 +0530 Subject: [PATCH] fix(pcie) : Enable Bridge Control SERR# for Type-1 functions Set Bridge Control SERR# Enable in val_pcie_enable_eru() for Type-1 functions so Root Ports can forward error messages. Signed-off-by: Sahil Shakil Malpekar Change-Id: I8c8705203e7103a5acebfa68481951c3b3506681 --- val/include/acs_pcie_spec.h | 1 + val/src/acs_pcie.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/val/include/acs_pcie_spec.h b/val/include/acs_pcie_spec.h index c8592ae7..bcd82620 100644 --- a/val/include/acs_pcie_spec.h +++ b/val/include/acs_pcie_spec.h @@ -156,6 +156,7 @@ #define TYPE1_P_MEM_LU 0x2C /* Prefetchable Limit Upper Offset */ /* Type 1 Bridge Control Register */ +#define BRIDGE_CTRL_SERRE_SET (1U << 17) #define BRIDGE_CTRL_SBR_SET 0x400000 /* Memory Base Reg Shifts */ diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c index 262bdf4e..2bb6a280 100644 --- a/val/src/acs_pcie.c +++ b/val/src/acs_pcie.c @@ -1267,6 +1267,13 @@ val_pcie_enable_eru(uint32_t bdf) dis_mask = (1 << CR_SERRE_SHIFT); val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | dis_mask); + /* Enable SERR# forwarding for functions with a Type 1 configuration header. */ + if (val_pcie_function_header_type(bdf) == TYPE1_HEADER) + { + val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); + val_pcie_write_cfg(bdf, TYPE01_ILR, reg_value | BRIDGE_CTRL_SERRE_SET); + } + /* Get the PCI Express Capability structure offset and * use that offset to read the Device Control register */