From 6249128440a4d6ad2a0cc4e7089c4c2282818dd2 Mon Sep 17 00:00:00 2001 From: Anish Nair Date: Mon, 5 Oct 2026 07:48:21 +0000 Subject: [PATCH] fix(val): correct page-table walk stride after partial top level When the initial translation level consumes fewer VA bits, only that level uses the partial index width. After descending to the next table, the walk must advance by the normal per-level width. Use bits_per_level instead of bits_at_this_level when updating bits_remaining in the MMU and page-table walkers. Change-Id: I263380beaf63f593dc7caf940f08c5bdbfe96c60 --- val/src/acs_mmu.c | 2 +- val/src/acs_pgt.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/val/src/acs_mmu.c b/val/src/acs_mmu.c index 0863a710..8cf97706 100644 --- a/val/src/acs_mmu.c +++ b/val/src/acs_mmu.c @@ -131,7 +131,7 @@ val_mmu_check_for_entry(uint64_t addr) /* update level and remaining VA bits to resolve */ ++this_level; - bits_remaining -= bits_at_this_level; + bits_remaining -= bits_per_level; bits_at_this_level = bits_per_level; } /* execution should don't reach here */ diff --git a/val/src/acs_pgt.c b/val/src/acs_pgt.c index 0499f3e3..59efabfd 100644 --- a/val/src/acs_pgt.c +++ b/val/src/acs_pgt.c @@ -333,7 +333,7 @@ uint64_t *val_find_pte(pgt_descriptor_t pgt_desc, uint64_t virtual_address) /* Move to the next level translation table */ tt_base_phys = val64 & (((0x1ull << (ias - page_size_log2)) - 1) << page_size_log2); ++this_level; - bits_remaining -= bits_at_this_level; + bits_remaining -= bits_per_level; bits_at_this_level = bits_per_level; } } @@ -755,7 +755,7 @@ uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_addr } tt_base_phys = val64 & (((0x1ull << (ias - page_size_log2)) - 1) << page_size_log2); ++this_level; - bits_remaining -= bits_at_this_level; + bits_remaining -= bits_per_level; bits_at_this_level = bits_per_level; } }