From 77565f49deddfc4fd83528d71b86d5f91722cb86 Mon Sep 17 00:00:00 2001
From: Aamir Abdul Azeez <165933255+aamir-azeez@users.noreply.github.com>
Date: Sun, 27 Sep 2026 00:00:56 -0400
Subject: [PATCH] Keep unconnected instance ports when generating Verilog

---
 .../test_from_verilog_unconnected_ports.py    | 45 +++++++++++++++++++
 veriloggen/verilog/to_verilog.py              |  2 +-
 2 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 tests/verilog/from_verilog_/unconnected_ports/test_from_verilog_unconnected_ports.py

diff --git a/tests/verilog/from_verilog_/unconnected_ports/test_from_verilog_unconnected_ports.py b/tests/verilog/from_verilog_/unconnected_ports/test_from_verilog_unconnected_ports.py
new file mode 100644
index 00000000..e60013a0
--- /dev/null
+++ b/tests/verilog/from_verilog_/unconnected_ports/test_from_verilog_unconnected_ports.py
@@ -0,0 +1,45 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import collections
+import io
+
+from pyverilog.vparser.parser import VerilogParser
+
+import veriloggen
+from veriloggen.verilog.from_verilog import VerilogReadVisitor
+
+
+def test_unconnected_instance_port(tmpdir):
+    veriloggen.reset()
+    source = '''
+module test;
+  wire CLK, RST;
+  adder u_adder (
+    .clk(CLK),
+    .rst(RST),
+    .B(1'b0),
+    .A()
+  );
+endmodule
+'''
+    parser = VerilogParser(outputdir=str(tmpdir), debug=False)
+    ast = parser.parse(source)
+    definitions = collections.OrderedDict(
+        (node.name, node) for node in ast.description.definitions)
+    visitor = VerilogReadVisitor(definitions)
+    visitor.visit(definitions['test'])
+
+    generated = visitor.converted_modules['test'].to_verilog()
+    reparsed = parser.parse(generated)
+    original_instance = definitions['test'].items[-1]
+    generated_instance = reparsed.description.definitions[0].items[-1]
+    original_tree = io.StringIO()
+    generated_tree = io.StringIO()
+    original_instance.show(buf=original_tree, showlineno=False)
+    generated_instance.show(buf=generated_tree, showlineno=False)
+    assert generated_tree.getvalue() == original_tree.getvalue()
+    ports = generated_instance.instances[0].portlist
+    assert [port.portname for port in ports] == ['clk', 'rst', 'B', 'A']
+    assert ports[2].argname.value == "1'b0"
+    assert ports[3].argname is None
diff --git a/veriloggen/verilog/to_verilog.py b/veriloggen/verilog/to_verilog.py
index 6e415c1f..56b3f459 100644
--- a/veriloggen/verilog/to_verilog.py
+++ b/veriloggen/verilog/to_verilog.py
@@ -767,7 +767,7 @@ def visit_Instance(self, node):
         module = node.module.name
         parameterlist = [vast.ParamArg(
             p, self.bind_visitor.visit(a)) for p, a in node.params]
-        portlist = [vast.PortArg(p, self.bind_visitor.visit(a))
+        portlist = [vast.PortArg(p, self.bind_visitor.visit(a) if a is not None else None)
                     for p, a in node.ports]
         name = node.instname
         instance = vast.Instance(module, name, portlist, parameterlist)