diff --git a/arch/tricore/include/irq.h b/arch/tricore/include/irq.h
index f4109c6f5bd72..f2ff77438c544 100644
--- a/arch/tricore/include/irq.h
+++ b/arch/tricore/include/irq.h
@@ -147,14 +147,14 @@
 /* FPU registers */
 
 #ifdef CONFIG_ARCH_TC1V6
-#  define FPU_SYNC_TRAP_REG  CPU_FPU_TRAP_CON
-#  define FPU_ASYNC_TRAP_REG CPU_FPU_TRAP_CON
+#  define FPU_SYNC_TRAP_REG   0xA000
+#  define FPU_ASYNC_TRAP_REG  0xA000
 #else
-#  define FPU_SYNC_TRAP_REG  CPU_FPU_SYNC_TRAP_CON
-#  define FPU_ASYNC_TRAP_REG CPU_FPU_TRAP_CON
+#  define FPU_SYNC_TRAP_REG   0xA030
+#  define FPU_ASYNC_TRAP_REG  0xA000
 #endif
-#define FPU_TRAP_FZE_SHIFT   20
-#define FPU_TRAP_TCL_SHIFT   1
+#define FPU_TRAP_FZE_SHIFT    20
+#define FPU_TRAP_TCL_SHIFT    1
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/tricore/src/Makefile b/arch/tricore/src/Makefile
index 524d0865428f8..3e28447cbfb20 100644
--- a/arch/tricore/src/Makefile
+++ b/arch/tricore/src/Makefile
@@ -239,7 +239,7 @@ distclean:: clean
 ifeq ($(BOARDMAKE),y)
 	$(Q) $(MAKE) -C board distclean
 endif
-	$(call DELFILE, $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds)
+	$(call DELFILE, $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds))
 	$(call DELFILE, Make.dep)
 	$(call DELFILE, .depend)
 
diff --git a/arch/tricore/src/common/tricore_fpu.c b/arch/tricore/src/common/tricore_fpu.c
index ec1c4343e9033..5b7c117d9c163 100644
--- a/arch/tricore/src/common/tricore_fpu.c
+++ b/arch/tricore/src/common/tricore_fpu.c
@@ -28,7 +28,7 @@
 
 #include <string.h>
 
-#include "tricore_internal.h"
+#include <arch/irq.h>
 
 /****************************************************************************
  * Public Functions
@@ -42,8 +42,8 @@ void tricore_fpuinit(void)
 {
   /* FPU zero-divide trap enable */
 
-  __mtcr(FPU_SYNC_TRAP_REG,
-         __mfcr(FPU_SYNC_TRAP_REG) | (1U << FPU_TRAP_FZE_SHIFT));
+  tricore_mtcr(FPU_SYNC_TRAP_REG, tricore_mfcr(FPU_SYNC_TRAP_REG) |
+                                  (1U << FPU_TRAP_FZE_SHIFT));
 }
 
 /****************************************************************************