From a1a9ac6cac4b92a4ba56da6834994d48616c36fa Mon Sep 17 00:00:00 2001
From: lfdevs <lfdevs@lfdevs.com>
Date: Sun, 27 Sep 2026 02:47:35 +0800
Subject: [PATCH] freedreno: add unofficial experimental support for Adreno 850

Add Adreno 850 device IDs for both the MSM DRM catalog and KGSL,
using the A8xx Gen2 and A840-derived configuration. Set the measured
highest bank bit fallback to 16 for kernels that do not expose it.

Accept KGSL UBWC 7.0 and map it to the existing A8xx 8-channel
configuration. Keep the A8xx register database synchronized with the
kernel catalog by adding the A850 CP, VSC, SP, and CX_MISC register
definitions.

This change intentionally leaves A850-specific GMU programming and MALU
support to the kernel and future Mesa changes.

Tested by building the aarch64 Mesa packages in the
termux-package-builder container and running glxinfo, vulkaninfo,
vkmark, and GMEM/SYSMEM offscreen tests on an Adreno 850 device.

Kernel patches can be found at: https://patchwork.freedesktop.org/series/174781/
---
 src/freedreno/common/freedreno_devices.py | 23 +++++++++++++++++++++++
 src/freedreno/registers/adreno/a6xx.xml   |  8 ++++++++
 src/freedreno/vulkan/msm_kgsl.h           |  1 +
 src/freedreno/vulkan/tu_knl_kgsl.cc       |  1 +
 4 files changed, 33 insertions(+)

diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index b1dfb7e601b3..921f039e3abf 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -1604,5 +1604,28 @@
         raw_magic_regs = a8xx_base_raw_magic_regs,
     ))
 
+add_gpus([
+        GPUId(chip_id=0x44051401, name="Adreno (TM) 850"), # DRM/MSM
+        GPUId(chip_id=0xffff44051401, name="Adreno (TM) 850"), # DRM/MSM fuse fallback
+        GPUId(chip_id=0xffff44051431, name="Adreno (TM) 850"), # KGSL
+    ], A6xxGPUInfo(
+        CHIP.A8XX,
+        [a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2,
+         GPUProps(shading_rate_matches_vk = True)],
+        num_ccu = 6,
+        num_slices = 3,
+        tile_align_w = 96,
+        tile_align_h = 32,
+        tile_max_w = 16416,
+        tile_max_h = 16384,
+        num_vsc_pipes = 32,
+        cs_shared_mem_size = 32 * 1024,
+        wave_granularity = 2,
+        fibers_per_sp = 128 * 2 * 16,
+        highest_bank_bit = 16,
+        magic_regs = dict(),
+        raw_magic_regs = a8xx_base_raw_magic_regs,
+    ))
+
 if __name__ == "__main__":
     main()
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index c26f1a950b7c..07e3ee9f4e2d 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -269,6 +269,7 @@ by a particular renderpass/blit.
 	<reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/>
 	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
 	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
+	<reg32 offset="0x084a" name="CP_MULTIDRAW_CNTL" variants="A8XX-"/>
 	<reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/>
 
 	<bitset name="a6xx_cp_protect_cntl" inline="yes">
@@ -1326,6 +1327,7 @@ by a particular renderpass/blit.
 
 	<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
 	<reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/>
+	<reg32 offset="0x0df8" name="VSC_VISIBILITY_FLUSH_CNTL" variants="A8XX-"/>
 	<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="cmd" variants="A6XX-A7XX">
 		<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
 		<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
@@ -4384,6 +4386,7 @@ by a particular renderpass/blit.
 	<reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/>
 	<reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/>
 	<reg32 offset="0xae0c" name="SP_STATUS"/>
+	<reg32 offset="0xae0e" name="SP_L0_PERF_TUNE" variants="A8XX-"/>
 
 	<reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init">
 		<!-- some perfcntrs are affected by a per-stage enable bit
@@ -4421,6 +4424,7 @@ by a particular renderpass/blit.
 
 	<reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/>
 	<reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/>
+	<reg32 offset="0xae14" name="SP_CHICKEN_BITS_5" variants="A8XX-"/>
 	<reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/>
 	<reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/>
 	<reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/>
@@ -5126,6 +5130,10 @@ by a particular renderpass/blit.
 	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
 	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
 	<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
+	<reg32 offset="0x0083" name="CX_MISC_GFX_PWR_CLK_STATUS" variants="A8XX-">
+		<bitfield name="GX_GDSC_POWER_OFF" pos="3" type="boolean"/>
+		<bitfield name="GX_CLK_OFF" pos="4" type="boolean"/>
+	</reg32>
 	<reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/>
 	<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
 		<bitfield pos="0" name="FASTBLEND" type="boolean"/>
diff --git a/src/freedreno/vulkan/msm_kgsl.h b/src/freedreno/vulkan/msm_kgsl.h
index 036be5ab25a9..0c4e13667dfc 100644
--- a/src/freedreno/vulkan/msm_kgsl.h
+++ b/src/freedreno/vulkan/msm_kgsl.h
@@ -249,6 +249,7 @@ enum kgsl_user_mem_type {
 #define KGSL_UBWC_4_0	4
 #define KGSL_UBWC_5_0	5
 #define KGSL_UBWC_6_0	6
+#define KGSL_UBWC_7_0	7
 
 /*
  * Reset status values for context
diff --git a/src/freedreno/vulkan/tu_knl_kgsl.cc b/src/freedreno/vulkan/tu_knl_kgsl.cc
index 2fa2ba34ef72..11916cca3eae 100644
--- a/src/freedreno/vulkan/tu_knl_kgsl.cc
+++ b/src/freedreno/vulkan/tu_knl_kgsl.cc
@@ -1961,6 +1961,7 @@ tu_knl_kgsl_load(struct tu_instance *instance, int fd)
    case KGSL_UBWC_4_0:
    case KGSL_UBWC_5_0:
    case KGSL_UBWC_6_0:
+   case KGSL_UBWC_7_0:
       device->ubwc_config.bank_swizzle_levels = 0x6;
       device->ubwc_config.macrotile_mode = FDL_MACROTILE_8_CHANNEL;
       break;