From 75480a6a4a81eb2d65e1e594848e37e385c847e8 Mon Sep 17 00:00:00 2001
From: Julia <juliaadod@gmail.com>
Date: Mon, 26 Oct 2026 08:35:50 +0300
Subject: [PATCH] bench: add riscv support to TIMFUNC

---
 demo/timing.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/demo/timing.c b/demo/timing.c
index a66ce8505..e365030da 100644
--- a/demo/timing.c
+++ b/demo/timing.c
@@ -66,6 +66,10 @@ static uint64_t TIMFUNC(void)
    unsigned hi, lo;
    __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
    return ((uint64_t)lo)|(((uint64_t)hi)<<32);
+#elif defined(__riscv) && __riscv_xlen == 64
+   uint64_t cycles;
+   __asm__ __volatile__ ("rdcycle %0" : "=r" (cycles));
+   return cycles;
 #else /* gcc-IA64 version */
    unsigned long result;
    __asm__ __volatile__("mov %0=ar.itc":"=r"(result)::"memory");