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[FMV] Add support for more features #444

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[FMV] Add support for more features
Lukacma Jul 16, 2026
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Add changelog
Lukacma Jul 16, 2026
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Add aditional features
Lukacma Aug 5, 2026
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Merge branch 'main' into main
Lukacma Aug 25, 2026
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Fix register checks and add new version
Lukacma Aug 25, 2026
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72 changes: 72 additions & 0 deletions main/acle.md
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Expand Up @@ -3102,6 +3102,31 @@ The following table lists the architectures feature mapping for AArch64.
| `FEAT_SME2` | sme2 | ```ID_AA64PFR1_EL1.SMEver >= 0b0001``` |
| `FEAT_MOPS` | mops | ```ID_AA64ISAR2_EL1.MOPS >= 0b0001``` |
| `FEAT_CSSC` | cssc | ```ID_AA64ISAR2_EL1.CSSC >= 0b0001``` |
| `FEAT_FP8` | fp8 | ```ID_AA64FPFR0_EL1.F8CVT == 0b1``` |

@CarolineConcatto CarolineConcatto Aug 26, 2026

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I've noticed that for FP8 the reference informs other system registers, should this be checked as well?
The following fields identify the presence of FEAT_FP8:
• ID_AA64FPFR0_EL1.F8CVT. • ID_AA64FPFR0_EL1.F8E4M3. • ID_AA64FPFR0_EL1.F8E5M2.

@Lukacma Lukacma Aug 26, 2026

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That is not necessary imo. Reading the spec for the F8CVT:

FEAT_FP8 implements the functionality identified by the value 1.

To me it means that when the value is 1 FEAT_FP8 is implemented

| `FEAT_F8F32MM` | f8f32mm | ```ID_AA64FPFR0_EL1.F8MM8 == 0b1``` |
| `FEAT_FP8DOT4` | fp8dot4 | ```ID_AA64FPFR0_EL1.F8DP4 == 0b1``` |
| `FEAT_FP8FMA` | fp8fma | ```ID_AA64FPFR0_EL1.F8FMA == 0b1``` |
| `FEAT_SME_F8F32` | sme-f8f32 | ```ID_AA64SMFR0_EL1.F8F32 == 0b1``` |
| `FEAT_SSVE_FP8DOT4` | ssve-fp8dot4 | ```ID_AA64SMFR0_EL1.SF8DP4 == 0b1``` |
| `FEAT_SSVE_FP8FMA` | ssve-fp8fma | ```ID_AA64SMFR0_EL1.SF8FMA == 0b1``` |
| `FEAT_SSVE_BitPerm` | ssve-bitperm | ```ID_AA64SMFR0_EL1.SBitPerm == 0b1``` |
| `FEAT_LUT` | lut | ```ID_AA64ISAR2_EL1.LUT >= 0b0001``` |
| `FEAT_FAMINMAX` | faminmax | ```ID_AA64ISAR3_EL1.FAMINMAX >= 0b0001``` |
| `FEAT_SME_LUTv2` | sme-lutv2 | ```ID_AA64SMFR0_EL1.LUTv2 == 0b1``` |
| `FEAT_SME2p1` | sme2p1 | ```ID_AA64PFR1_EL1.SME >= 0b0001 && ID_AA64SMFR0_EL1.SMEver >= 0b0010```|
| `FEAT_SME2p2` | sme2p2 | ```ID_AA64PFR1_EL1.SME >= 0b0001 && ID_AA64SMFR0_EL1.SMEver >= 0b0011```|
| `FEAT_SVE2p1` | sve2p1 | ```ID_AA64PFR0_EL1.SVE >= 0b0001 && ID_AA64ZFR0_EL1.SVEver >= 0b0010```|
| `FEAT_SVE2p2` | sve2p2 | ```ID_AA64PFR0_EL1.SVE >= 0b0001 && ID_AA64ZFR0_EL1.SVEver >= 0b0011```|
| `FEAT_SME_F16F16` | sme-f16f16 | ```ID_AA64SMFR0_EL1.F16F16 == 0b1``` |
| `FEAT_GCS` | gcs | ```ID_AA64PFR1_EL1.GCS >= 0b0001``` |
| `FEAT_D128` | d128 | ```ID_AA64MMFR3_EL1.D128 >= 0b0001``` |
| `FEAT_FP8DOT2` | fp8dot2 | ```ID_AA64FPFR0_EL1.F8DP2 == 0b1``` |

@CarolineConcatto CarolineConcatto Aug 26, 2026

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Do you mind moving this close to FEAT_FP8DOT4

| `FEAT_SME_F8F16` | sme-f8f16 | ```ID_AA64SMFR0_EL1.F8F16 == 0b1``` |
| `FEAT_F8F16MM` | f8f16mm | ```ID_AA64FPFR0_EL1.F8MM4 == 0b1``` |
| `FEAT_SVE_AES2` | sve-aes2 | ```ID_AA64ZFR0_EL1.AES >= 0b0011``` |
| `FEAT_SVE_BFSCALE` | sve-bfscale | ```ID_AA64ZFR0_EL1.B16B16 >= 0b0010``` |
| `FEAT_SVE_F16F32MM` | sve-f16f32mm | ```ID_AA64ZFR0_EL1.F16MM >= 0b0001``` |
| `FEAT_SME_MOP4` | sme-mop4 | ```ID_AA64SMFR0_EL1.SMOP4 == 0b1``` |

The tables are sorted by priority, starting from features of lowest priority ending with features of highest priority.

Expand Down Expand Up @@ -3169,6 +3194,31 @@ unless otherwise specified.
| rdma | **202410** |
| mops | 202410 |
| cssc | **202520** |
| fp8 | **202690** |
| f8f32mm | 202690 |
| fp8dot4 | 202690 |
| fp8fma | 202690 |
| sme-f8f32 | 202690 |
| ssve-fp8dot4 | 202690 |
| ssve-fp8fma | 202690 |
| ssve-bitperm | 202690 |
| lut | 202690 |
| faminmax | 202690 |
| sme-lutv2 | 202690 |
| sme2p1 | 202690 |
| sme2p2 | 202690 |
| sve2p1 | 202690 |
| sve2p2 | 202690 |
| sme-f16f16 | 202690 |
| gcs | 202690 |
| d128 | 202690 |
| fp8dot2 | 202690 |
| sme-f8f16 | 202690 |
| f8f16mm | 202690 |
| sve-aes2 | 202690 |
| sve-bfscale | 202690 |
| sve-f16f32mm | 202690 |
| sme-mop4 | 202690 |

### Dependencies

Expand Down Expand Up @@ -3214,6 +3264,28 @@ The following table lists the feature dependencies for AArch64.
| sme-f64f64 | sme |
| sme-i16i64 | sme |
| sme2 | sme |
| fp8 | simd |
| f8f32mm | simd, fp8 |
| fp8dot4 | fp8 |
| fp8fma | fp8 |
| sme-f8f32 | sme2, fp8 |
| ssve-fp8dot4 | sme2, fp8 |

@CarolineConcatto CarolineConcatto Aug 25, 2026

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Why do new need the ssve- features? I would imagine we could still have them generated with +sme2 and the sve feature. Am I missing something?

@Lukacma Lukacma Aug 26, 2026

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Sure we could them generated like that, but that is only true for cores which have both non-ssve and ssve feature. If core supports only ssve variant that function version wouldn't be emitted.

| ssve-fp8fma | sme2, fp8 |
| ssve-bitperm | sme2 |

@CarolineConcatto CarolineConcatto Aug 25, 2026

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Should this be sme2,sve-bitperm

def FeatureSSVE_BitPerm : ExtensionWithMArch<"ssve-bitperm", "SSVE_BitPerm", "FEAT_SSVE_BitPerm",
  "Enable Armv9.6-A SVE BitPerm support in streaming SVE mode", [FeatureSME2, FeatureSVEBitPerm]>;

@Lukacma Lukacma Aug 26, 2026

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We don't have sve-bitperm feature in FMV. We have sve2-bitperm, which enables both sve2 and sve-bitperm feature and is not a dependency of ssve-bitperm.

| lut | simd |
| faminmax | simd |
| sme-lutv2 | sme2 |
| sme2p1 | sme2 |
| sme2p2 | sme2p1 |
| sve2p1 | sve2 |
| sve2p2 | sve2p1 |

@AlfieRichardsArm AlfieRichardsArm Jul 20, 2026

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Not a bug, but I do wonder

As sve2p2 requires armv9.5 is it worth (for FMV) implying everything thing that armv9.5 implies? That is not something we do for architecture options but it feels like there may be more to loose with FMV as it is more likely to be enabled via target_version (sve2p2) as opposed to -march-armv9.5-a+sve2p2 or -mcpu?

@Lukacma Lukacma Jul 27, 2026

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My main concern with this is that we can have situations where features added as optional from certain version will be moved and added as optional from earlier architecture versions in later releases.

| sme-f16f16 | sme2 |
| d128 | lse |

@CarolineConcatto CarolineConcatto Aug 25, 2026

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Should this be lse128?
At least that is what I see in the compiler:

def FeatureD128 : ExtensionWithMArch<"d128", "D128",
  "FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128",
  "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
  "and instructions",
  [FeatureLSE128]>

@Lukacma Lukacma Aug 26, 2026

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We don't have lse128 feature in FMV as we internally agreed to add features which introduce new builtins and intrinsics. So I went for indirect dependency here as lse128 requires lse.

| fp8dot2 | fp8 |
| sme-f8f16 | sme2, fp8 |
| f8f16mm | simd, fp8 |
| sve-f16f32mm | sve |
| sme-mop4 | sme2 |

### Selection

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