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fix(pcie) : Enable Bridge Control SERR# for Type-1 functions #595

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Merged
chetan-rathore merged 1 commit into from
Oct 6, 2026
Merged

fix(pcie) : Enable Bridge Control SERR# for Type-1 functions #595

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1 change: 1 addition & 0 deletions val/include/acs_pcie_spec.h
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Original file line number Diff line number Diff line change
Expand Up @@ -156,6 +156,7 @@
#define TYPE1_P_MEM_LU 0x2C /* Prefetchable Limit Upper Offset */

/* Type 1 Bridge Control Register */
#define BRIDGE_CTRL_SERRE_SET (1U << 17)
#define BRIDGE_CTRL_SBR_SET 0x400000

/* Memory Base Reg Shifts */
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7 changes: 7 additions & 0 deletions val/src/acs_pcie.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1267,6 +1267,13 @@ val_pcie_enable_eru(uint32_t bdf)
dis_mask = (1 << CR_SERRE_SHIFT);
val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | dis_mask);

/* Enable SERR# forwarding for functions with a Type 1 configuration header. */
if (val_pcie_function_header_type(bdf) == TYPE1_HEADER)
{
val_pcie_read_cfg(bdf, TYPE01_ILR, &reg_value);
val_pcie_write_cfg(bdf, TYPE01_ILR, reg_value | BRIDGE_CTRL_SERRE_SET);
}

/* Get the PCI Express Capability structure offset and
* use that offset to read the Device Control register
*/
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