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13 changes: 9 additions & 4 deletions .claude/board/LATEST_STATE.md
Original file line number Diff line number Diff line change
@@ -1,9 +1,14 @@
## 2026-09-16 — PR #1241 merged (`d5d3f7ab`): the facet's per-axis LCP is one masked register readout — NO contract inventory delta

`FacetCascade::hi_distance` / `lo_distance` now read `tz((a ^ b) & AXIS_BYTES)
/ 16` off the `u128` instead of gathering a six-byte chain and walking it:
12.5 → 5.8 ns for both axes, bit-identical over 64K pairs, disable-verified.
No public type added or removed; two private consts + one private `const fn`.
`FacetCascade::hi_distance` / `lo_distance` now read
`(tz((a ^ b) & AXIS_BYTES) − 32) / 16` off the `u128` — the 32 classid bits
sit below the tiers, so the subtraction is load-bearing: without it a tier-0
divergence reads as prefix 2, not 0 (Codex on #1242 caught the formula as
first written here, which omitted it; the merged code always had it) —
instead of gathering a six-byte chain and walking it: 12.5 → 5.8 ns for both
axes, bit-identical over 64K pairs, disable-verified. No public type added or
removed; two private consts + two private `const fn`s (`tier_byte_mask`,
`shared_axis` — "one" as first written here was wrong, same review).
Arc entry in `PR_ARC_INVENTORY.md`; the fold-once epiphany
(`E-FORMAT-SLOT-FOLD-IS-THE-SAME-OP-AS-THE-VL-DESCENT-1`) landed with the PR.
Sibling measurements the same day: ndarray #311 (ternlogq tail descent 5–8×;
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9 changes: 9 additions & 0 deletions .claude/board/PR_ARC_INVENTORY.md
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Expand Up @@ -9,6 +9,15 @@
identical case. Board: `E-FORMAT-SLOT-FOLD-IS-THE-SAME-OP-AS-THE-VL-DESCENT-1`.
2 files, 3 commits (the first cut re-folded the gathered chain into a
`u64` — 1.5×; the operator's *"fold the PowerShell logic once"* replaced it).
- *Correction 2026-09-16 (Codex on #1242):* **4 commits**, not 3 —

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P2 Badge Correct the remaining axis-prefix formula

This appended correction fixes only the commit count, while the same entry’s Locked statement at lines 15–17 still records tz((a ^ b) & AXIS_BYTES) / 16 without the required − 32. A consumer relying on this canonical arc entry would therefore still compute a tier-0 divergence as prefix 2, contradicting both shared_axis and the corrected LATEST_STATE.md; append a corresponding formula correction here as well.

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Correct — the same omission sat in the arc entry's Locked line and I only fixed LATEST_STATE. Appended a second dated correction to the #1241 entry recording (tz((a ^ b) & AXIS_BYTES) − 32) / 16 and why the offset matters; the original line stays as written per the append-only rule.


Generated by Claude Code

`95e2863` (u64 fold), `ce6664e` (epiphany entry), `76bb237` (masked
single-register readout), `45c5199` (entry corrected to the readout).
- *Correction 2026-09-16 (Codex on #1243):* the **Locked** line below
reads `tz((a ^ b) & AXIS_BYTES) / 16` — it omits the `− 32` for the four
classid bytes below the tiers. The merged `shared_axis` is
`(tz((a ^ b) & AXIS_BYTES) − 32) / 16`; without the offset a tier-0
divergence would read as prefix 2, not 0. The line itself stays as
written (append-only); this note is the record.
- **Locked:** *the register is already the formatted form; never un-format it
to compute on it.* An axis prefix is `tz((a ^ b) & AXIS_BYTES) / 16` past
the classid — the same op as the whole-facet `prefix_distance`.
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