G1 and G2's pending falsifiers, RUN — and G2's answer is tier-dependent - #310
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…dependent `masking-ops-state.md` listed two measurements as PENDING and this probe as the instrument for both. Both are now run against the real 12 408-op x86-64 lift. THE BLOCKER WAS STALE, and that is the first finding. The doc read "that probe needs a Win32 PE binary; none exists in this container." One does: r2sleigh/probes/win32-census/legacy_app.exe, 130 613 bytes, committed since 2026-08-27. No synthetic dump was needed. Same shape as the neon-qemu "missing target" that was a missing linker: a report of absence is not evidence of it. G1's second half — ANSWERED. Native eq_u8 vs the widening workaround it replaced: 8.7x on v4, 14x on v3 (34.4x / 26.1x against scalar). The 26-34x is the expected lane count, not an anomaly, and must not be compared to G1's own 6.91x — that pair is u8-vectorized vs i32-vectorized, this one is scalar vs vectorized. Bandwidth corroborates: 52 GB/s L1-resident vs 2 GB/s scalar. G2 — ANSWERED, and TIER-DEPENDENT. The same native find_ram_in_range arm is a 1.51x WIN on AVX-512 and a 0.55x LOSS on AVX2. This file predicted the mechanism (only avx512 epu64 and NEON cmhi have the instruction; avx2/scalar are flat polyfills); the measurement puts a number on it — on v3 the native path is a scalar loop wearing a vector signature and loses to the scalar baseline. Consumers on a v3 floor keep the hi32/lo32 split. Two corrections to PR #308, both of which move a number: - It measured v3/AVX2 while the report implied AVX-512. .cargo/config.toml is x86-64-v3; the host carrying avx512f says nothing about what was compiled. Every arm now runs under both configs and the program prints its own realization line. - No black_box. ndarray's own G1 figures were published 8.06x/6.75x and corrected to 6.91x/5.84x for exactly this. Inputs AND outputs are now protected on every arm, all or none. And the widening tax was real for u8 but NEVER existed for u64: offset read twice is 16 B/op, hi32+lo32 read twice is also 16 B/op. Splitting a u64 into two u32s does not add traffic, it halves the element width — which is why the widened arms beat the native one on v3. #308's crossover number survives; its stated mechanism does not. Unchanged: every arm degrades to <=1.0x above ~200 K ops on both tiers, and the consumer verdict holds — 3 us saved on a binary whose SLEIGH lift costs milliseconds. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCfrD5y19cvFc4AoyydXYv
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Included review availability: 1 review is currently available. Your included PR review attempts over the past 7 days set your current allowance at 3 reviews per hour. 📝 WalkthroughWalkthroughThe probe adds native ChangesNative masking comparison probe
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~20 minutes Change: Other Merge Risk: ⚪ Minimal · up to The updated measurement notes consistently correct the split-u64 traffic calculation without changing executable behavior. No merge-blocking risk is established. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
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The arms table promises to describe every validated arm and listed only S/AND/TERN/UNDER, so a reader could not reconstruct the five-arm methodology or its pass counts from the docs. Adds NATIVE with its three predicate passes plus the mask combination (4 total). Two things the finding did not name, fixed with it because they are the same staleness: - The gap section still read "two primitive gaps this probe had to work around" in the present tense, and closed on "a general range needs the primitive" — both contradicted by the Measured section a few lines below, which reports the primitives shipped and measured. Re-framed as what the FIRST run found (the widened arms still exist and still need their rationale) with the closure stated inline. - The other four rows did not say their columns are WIDENED, which is the whole reason NATIVE is a different arm rather than a faster spelling of the same one. Named in each row. Gates: clippy -D warnings (v4 config), cargo fmt --check, and `cargo test --no-run --no-default-features` — the job that went red on #308 for a missing required-features gate. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCfrD5y19cvFc4AoyydXYv
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In `@examples/r2il_column_scan_probe.rs`:
- Around line 120-124: Correct the Q2 traffic accounting in both records and the
surrounding explanation: describe NATIVE as 17 bytes per logical row (one u8
space plus two u64 offset reads), widened AND/TERN/split inputs as 16 bytes
(space32, hi32, and two lo32 values), and split offset predicates as 12 bytes
plus the 4-byte space32 predicate. Explicitly include the u8-to-u32 widening
cost, note possible mask-gated loads in the _under path, and retain AVX2/AVX-512
guidance based on measured timings and native-path generality rather than equal
traffic.
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… not parity coderabbit finding, verified by counting the arms directly. The claim published in 4437896's parent was "offset read twice is 16 B/op, and hi32+lo32 read twice is also 16 B/op", concluding the Q2 arms paid no widening tax at all. hi32 is read ONCE, not twice. Counted: NATIVE space 1 B + offset 8 B (ge) + offset 8 B (lt) = 17 B/op AND / TERN space32 4 B + hi32 4 B + lo32 4 B + lo32 4 B = 16 B/op Offset-derived alone it is 16 B native vs 12 B split — a 25% saving, not parity, because each split predicate touches only the half it needs while every native u64 predicate pulls all eight bytes. So the split halves the element width AND cuts traffic; the widened path reads strictly less than the native one on both counts. The DIRECTION is unchanged and was never in doubt: widened beats native on v3, matches on v4, which is what the measured timings show. What was wrong is the mechanism offered for it. The consumer guidance now rests on the timings and the native path's generality (no hi32 bucket assumption), never on the retired equal-traffic claim. The u8 half of that section stands and gains its contrast: widening tag/space to u32 is a real 4x tax with no compensating structure — opposite sign to the u64 case, which is why one framing could not cover both. Corrected in both records (the probe doc and masking-ops-state.md), each marked as superseding its own earlier text rather than replacing it silently. Gates: clippy -D warnings (v4 config), cargo fmt --check, cargo test --no-run --no-default-features. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCfrD5y19cvFc4AoyydXYv
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masking-ops-state.mdlisted two measurements as PENDING and named this probe as the instrument for both. Both are now run, against the real 12 408-op x86-64 lift — not a synthetic stream.The blocker was stale, and that is the first finding
The doc read: "that probe needs a column dump from
r2sleigh-lift'swin32_census, which needs a Win32 PE binary; none exists in this container."One does —
r2sleigh/probes/win32-census/legacy_app.exe, 130 613 bytes, committed since 2026-08-27. No synthetic dump was needed. Same shape as theneon-qemu"missing target" that turned out to be a missing linker: a report of absence is not evidence of absence.G1's second half — ANSWERED, decisively
eq_u32eq_u8The native primitive beats the widening workaround it replaced by 8.7× (v4) / 14× (v3).
The 26-34× against scalar is the expected lane count, not an anomaly — 32-64 bytes per instruction against a 1-byte scalar loop — and bandwidth corroborates it (52 GB/s L1-resident vs 2 GB/s scalar). It must not be compared to G1's own 6.91×: that pair is u8-vectorized vs i32-vectorized, this one is scalar vs vectorized. I nearly discarded the result on that mistaken comparison.
G2 — ANSWERED, and the answer is TIER-DEPENDENT
The same native
find_ram_in_rangearm (eq_u8+ge_u64+lt_u64+AND3), 12 408 ops:masking-ops-state.mdpredicted the mechanism — "only avx512 (epu64) and NEON (cmhi) have the instruction; scalar/avx2 are flat polyfills" — and this puts a number on it. On v3 the native path is a scalar loop wearing a vector signature, and it loses to the scalar baseline it was meant to replace.Consumer consequence: on an AVX2 floor, keep the hi32/lo32 split; on v4 the native spelling is both faster and general (no bucket assumption).
Two corrections to PR #308, both of which move a number
.cargo/config.tomlisx86-64-v3; the host carryingavx512fsays nothing about what was compiled. Every arm now runs under both configs, and the program prints its own realization line.black_box. ndarray's own G1 figures were published 8.06×/6.75× and corrected to 6.91×/5.84× for exactly this. Inputs and outputs are now protected on every arm — all or none, since the asymmetry is the trap.And the widening tax was real for u8 but never existed for u64
#308 blamed its Q2 crossover on widened columns. Measured, the Q2 arms never paid one:
offsetread twice is 16 B/op, andhi32+lo32read twice is also 16 B/op. Splitting a u64 into two u32s does not add traffic — it halves the element width, which is what the vector units reward, and is why the widened arms beat the native one on v3. #308's crossover number survives; its stated mechanism does not.What did not change
Every arm still degrades to ≤ 1.0× above ~200 K ops on both tiers, and the consumer verdict is unmoved: a whole-census
find_ram_in_rangeis ~9.0 µs scalar vs ~5.9 µs native-on-v4 — 3 µs on a binary whose SLEIGH lift costs milliseconds. The primitive surface changed; a word-level op pays for the span it is given did not.Docs + one example. No primitive added, no default changed, nothing outside
examples/and.claude/.🤖 Generated with Claude Code
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