A general purpose language for safer, yet expressive hardware design.
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Anvil is a general-purpose hardware description language (HDL) that gives designers control over registers and clock-cycle latency. Its type system ensures that values are used only while valid and that registers are not overwritten while still in use. This property is called timing safety and is enforced at compile time.
Anvil designs compile to synthesizable SystemVerilog.
| Type system | RTL expressiveness | Hardware efficiency |
|---|---|---|
| Anvil's type system enforces timing safety modularly. | Designers control registers and cycle-level latency. | Anvil designs add no clock-cycle latency and have minimal overhead in area, power, and frequency. |
Run a program in the online playground, work through the tutorial, or install the compiler. The language reference covers syntax and semantics.
- Anvil compiler — The compiler, tests, and example hardware designs.
- Language server — Experimental language support and editor extensions for VS Code and Vim/Neovim.
- Documentation — The source for the documentation site, tutorial, and language reference.
- Evaluation experiments — Evaluation designs, test harnesses, synthesis reports, and reproduction instructions.
- RISCy experiment — A simple pipelined RISC-V processor written in Anvil.
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Jason Zhijingcheng Yu, Aditya Ranjan Jha, Umang Mathur, Trevor E. Carlson, and Prateek Saxena. 2026. Anvil: A General-Purpose Timing-Safe Hardware Description Language. In Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’26). Association for Computing Machinery. DOI: 10.1145/3779212.3790125.
For discussions please join AnvilHDL Zulip community. Report bugs or propose changes through the compiler, language server, or documentation issue trackers. Contributions are welcome.
For collaborations or queries, please reach out to one of the maintainers:
