research: stop the one-XOR shear carrier on a lossless integer payload

research/sl2z-payload-encoder-stop/README.md

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+# The one-XOR shear carrier does not encode integer B
+
+**Negative stop on a lossless payload. No new κ.** Selected κ stays
+`0.001672660197076918`.
+
+## Question
+
+PR #3905 shows that `B = X²Y²` needs four calls in the formal shear alphabet.
+PR #3947 shows that a three-bit quotient sends that same `B` to one XOR,
+`b ^= c`, and that this quotient is not a faithful encoding of the integer
+matrices. Discussion reply 19032401 asks for the next piece, not another formal
+word: name a payload subspace and an injective encoder/decoder/consumer, prove
+the commuting diagram, and price conversion, storage, and dirty return.
+**Stop if that caller already has the one-XOR endpoint.**
+
+This package answers that stop. It does not redo the faithful-word moment test
+`M(a) < 1`.
+
+## Result
+
+Let
+
+```text
+X = [[1, 1], [0, 1]],  Y = [[1, 0], [1, 1]],  B = X²Y² = [[5, 2], [2, 1]].
+```
+
+`B² − I = [[28, 12], [12, 4]]`. Its only integer kernel vector is `0`, because
+`12x + 4y = 0` forces `y = −3x` and then `28x + 12y = −8x = 0`. The gcd of the
+four entries is 4, so `B² ≡ I` modulo `M` only for `M` dividing 4.
+
+The projective action of these matrices modulo 3, restricted to the sum-zero
+plane in `F₂⁴`, reproduces the published carrier
+
+```text
+ρ(B) = [[1, 0, 0], [0, 1, 1], [0, 0, 1]],
+```
+
+which is `b ^= c` on column vectors and has order 2. `ρ(X³) = I` while
+`X³ = [[1, 3], [0, 1]] ≠ I`, so the carrier is not an injective encoding of
+the integer generators.
+
+**Integer payload.** A map of order 2 cannot intertwine with `B` on a
+`B`-invariant subset `S ⊆ ℤ²` through an injective encoder, except `S ⊆ {0}`.
+One use of the 3-bit block distinguishes at most 8 payloads, and one use of
+the 6-bit two-block caller at most 64. The box `{0, …, 2ᵐ − 1}²` exceeds 8
+states at `m ≥ 2` and exceeds 64 states at `m ≥ 4`. Under the identity 4-bit
+packing, `(1, 0) ↦ (5, 2)` has Hamming distance 2, so it is not one XOR.
+
+**Mod-4 quotient.** This is the largest modulus on which `B² = I`. The action
+has 4 fixed points and 6 transpositions, which would fit the cycle type of the
+6-bit caller as a lookup. No wiring does so: every placement of the four
+address bits into `(a, b, c, p, q, r)`, with the other two bits constant,
+fails to realize `B` mod 4 after `b ^= c`. The Boolean map itself is the
+linear circuit
+
+```text
+(x0, x1, y0, y1) ↦ (x0, x1 XOR y0, y0, x0 XOR y1)
+```
+
+with **two XORs**, no AND, and no use of the carrier. Those two output parities
+use disjoint inputs, so two XORs is the XOR count of this circuit. Routing the
+same map through the carrier cannot undercut a circuit that does not need that
+extra XOR.
+
+**Exact legal caller.** On an `m`-bit nonnegative address, `Y, Y, X, X`
+overwrites the pair by `B`. Each step is one integer addition. A fixed
+full-adder of `W` bits, final carry required to be 0, costs `2W` XOR, `2W`
+AND and `W` OR. The four widths are `m+1`, `m+2`, `m+2` and `m+3`, so the bill
+is
+
+```text
+XOR = 8m + 16,   AND = 8m + 16,   OR = 4m + 8.
+```
+
+The input address is consumed. Restoring it costs a clean copy, `2m` further
+XORs, and `2m` stored bits. The adder carry returns to 0. There is no spectator
+role in this address model. For `m = 4` the consuming bill is 48 XOR, 48 AND
+and 24 OR, against one incorrect carrier XOR.
+
+Checked for every pair at `m = 1..5`, and at the `m = 8` corner
+`(255, 255)`.
+
+## What this does not claim
+
+No supplier, no group-algebra register, no selected cold replay, and no κ.
+The mod-4 two-XOR circuit is a quotient, not an implementation of integer `B`.
+A lookup table whose cycle type embeds into the 6-bit caller is not a legal
+free conversion. Unknown gate-sharing across a different alphabet is not priced
+as zero.
+
+## Reproduce
+
+```sh
+python3.12 -B scripts/research_package.py --package research/sl2z-payload-encoder-stop
+```
+
+Expected first line:
+
+```text
+PASS_SL2Z_PAYLOAD_ENCODER_STOP ... wiring_hits=0 mod4_direct_xor=2 ... no_new_kappa=true
+```
+
+Standard library only. Base `bb4bccbf42844d2801487450727c2f63e10d1d0f`.
+Priority revision 6.
+
+## Open next questions
+
+Can the low two bits of an exact `m`-bit address use the mod-4 two-XOR map
+while a carry into the high half replaces one of the four additions? The first
+step is one shear's high-half recurrence on a single `m = 4` witness. It is
+blocked if that carry is itself an addition: the split then does not beat
+`8m + 16` XORs plus the matching ANDs and ORs.
+
+## Credit
+
+PR #3905 (1337isnot1337 / OpenAI Codex) for the integer shear target and the
+four-call formal minimum. PR #3937 and PR #3947 (ToikY / OpenAI Codex) for the
+commutative obstruction, the three-bit carrier, the one-XOR invoice, and the
+payload question in discussion reply 19032401. The kernel argument, the wiring
+exhaustion, the two-XOR quotient circuit, and the fixed-width adder bill are
+new here.
+
+Prepared by unpaidmoon with substantial Cursor Grok 4.7 assistance. Apache-2.0.

research/sl2z-payload-encoder-stop/SOURCES.json

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+{
+  "schema_version": 1,
+  "base_commit": "bb4bccbf42844d2801487450727c2f63e10d1d0f",
+  "files": [
+    {
+      "path": "certificates/selected-result.json",
+      "usage": "provenance",
+      "git_blob": "b1fea0c94436b236cc2b7d41a7be032811b94c81",
+      "sha256": "bb2eaa58647b353f88d0aec2eafb9d30df1be53589231b23e12ceef3e4bad129"
+    },
+    {
+      "path": "docs/research/agent-task-catalog.json",
+      "usage": "provenance",
+      "git_blob": "67f085acd86acd7d4e03922d9cf4b26bca66fed5",
+      "sha256": "47b42433f5a85809a3aadd29c2c339da2c6ed728e4f7762df6b88bccb7874cf0"
+    }
+  ]
+}

research/sl2z-payload-encoder-stop/TASK.json

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+{
+  "schema_version": 1,
+  "task_id": "bit-new-register-model",
+  "priority_revision": 6,
+  "base_commit": "bb4bccbf42844d2801487450727c2f63e10d1d0f",
+  "original_card": {
+    "id": "bit-new-register-model",
+    "question": "Can an explicitly larger or nonabelian register model escape the scoped three-register obstruction?",
+    "starting_points": [
+      "docs/research/research-family-status.md",
+      "research/bit-three-register-lower-bound/README.md",
+      "certificates/selected-result.json",
+      "research/bit-gl3-mixed-targets-length10/README.md",
+      "docs/research/community-efficient1000-review.md"
+    ],
+    "methods": [
+      "Construct the smallest exact identity in a newly specified legal operation alphabet.",
+      "Derive a target-specific relaxation bound for that same explicit alphabet."
+    ],
+    "acceptance_gate": "Name the changed hypothesis, all counted roles and a uniform identity; finite column tests alone do not certify it. A scoped local result may be retained without a complete supplier. Expanding it into further construction rounds requires the family-level budget and obligation gate in research-family-status.md; an optimistic passing relaxation alone is not acceptance.",
+    "first_step": {
+      "command": [
+        "python3",
+        "-B",
+        "scripts/research_baseline.py"
+      ],
+      "expected": "PASS_RESEARCH_BASELINE_BINDINGS_ONLY",
+      "inspect": "Read Model section 1 of the three-register bound and identify the exact excluded free operations.",
+      "scope": "Positive control / source-bound orientation only; this is not a new construction or full cold replay."
+    },
+    "first_experiment": "First compare the alphabet, role count and length with the fully replayed #1974 census and #2027 mixed-root tariff. Identify a changed premise and a legal native implementation; then price one smallest completed instance before searching larger words.",
+    "bottleneck_link": "A small-width completed saving changes the bit primitive; a finite-address identity alone is insufficient.",
+    "allowed_variations": [
+      "Choose a fixed larger register count or a specified nonabelian operation family."
+    ],
+    "scope_change_triggers": [
+      "Remaining inside the already-excluded three-register abelian model.",
+      "Repeating the two-register GL3 census or a covered three-register length without changing a hypothesis; a formal group-algebra word without native conversion is a partial result."
+    ],
+    "overlap_terms": [
+      "three-register",
+      "nonabelian",
+      "group algebra"
+    ]
+  },
+  "scope_status": "changed",
+  "actual_scope": "Does PR #3947's one-XOR carrier already implement a lossless payload for B=X^2 Y^2, and what does a legal exact address caller cost instead?",
+  "scope_change_reason": "The card asks for a new nonabelian register alphabet that might escape the three-register bound. This package does not search a new word. It takes the payload-encoder half of the #3947 handoff (discussion reply 19032401), which is item 5 of this session's ordered open-handoff list, and stops where that handoff says to stop: the one-XOR endpoint is not a lossless implementation of the integer target. The separate moment inequality M(a)<1 for faithful shear words is a different piece and is not redone.",
+  "bottleneck_link": "Side result. A three-bit image of B does not become a cheaper bit primitive unless a lossless payload encoder is priced. This prices that encoder as absent for integer addresses and records the four-addition bill. No selected-supplier term changes.",
+  "budget_minutes": 60,
+  "stop_rule": "Stop when the one-XOR carrier either implements a named injective payload or is shown not to. Do not search a larger formal word, and do not treat the mod-4 quotient as the integer target.",
+  "outcome": "negative-result",
+  "evidence": "Independent standard-library checks: B^2-I has trivial integer kernel, the recomputed carrier is the single XOR b^=c of order 2, identity packing of (1,0) to (5,2) has Hamming distance 2, no wiring into the six-bit caller realizes B mod 4, and four fixed-width additions realize exact B.",
+  "author": "unpaidmoon",
+  "ai_assistance": "Cursor Grok 4.7 drafted the package, the obstruction argument, and the verifier. The mathematics was checked by running that verifier.",
+  "open_questions": [
+    {
+      "question": "Can the low two bits of an exact m-bit address use the mod-4 two-XOR map while a carry into the high half replaces one of the four additions?",
+      "why_it_matters": "The mod-4 quotient costs two XORs and no ANDs. If its carry into the remaining bits still costs an addition, the split does not beat the four-addition bill.",
+      "first_step": "Write the high-half recurrence for one shear, with the low limb reduced mod 4, and count additions plus the two XORs on a single m=4 witness.",
+      "blocked_by": "A carry that is itself an m-bit addition makes the split pointless; that comparison has not been expanded into a second package."
+    }
+  ]
+}

research/sl2z-payload-encoder-stop/VERIFY.json

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+{
+  "schema_version": 1,
+  "status": "ready",
+  "python": "3.12",
+  "requirements": [],
+  "inputs": [],
+  "commands": [
+    {
+      "argv": [
+        "{python}",
+        "-B",
+        "{package}/verify.py"
+      ],
+      "timeout_seconds": 120,
+      "checks": "Integer kernel of B^2-I, carrier XOR recomputation, Hamming witness, mod-4 wiring exhaustion, direct two-XOR quotient, and fixed-width four-addition bill"
+    }
+  ]
+}