Pinned Loading

1. BFloat16 BFloat16 Public

   RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

   Verilog 26 1

2. Systolic_MAC_with_DFT Systolic_MAC_with_DFT Public

   GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure

   Verilog 60 1

3. blake2_asic blake2_asic Public

   SKY130A implementatoin of the Blake2s hash algorithm

   Verilog 25 1

4. Systolic_Array_with_DFT_v2 Systolic_Array_with_DFT_v2 Public

   IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

   Verilog 39 3

5. Nasdaq-HFT-FPGA Nasdaq-HFT-FPGA Public

   RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.

   C 107 27

6. Expresso_ASIC_Chip Expresso_ASIC_Chip Public

   Full chip tapeout of the unmanaged cut-through 100Mbps Ethernet switch and the Head Death of the Universe beacon. Targetting 0.5x0.5 waffer.space run#2.

   Python 4