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1. AXI4_PROTOCOL AXI4_PROTOCOL Public

   Parameterized AXI4 Slave RTL in SystemVerilog implementing independent read and write paths. Supports AW/W FIFOs, burst transfers (FIXED/INCR/WRAP), outstanding read transactions, slot-based read F…

   SystemVerilog

2. APB_PROTOCOL APB_PROTOCOL Public

   A complete AMBA APB (Advanced Peripheral Bus) verification environment developed using SystemVerilog and UVM

   Verilog

3. uvm-reusable-vip uvm-reusable-vip Public

   SystemVerilog

4. synchronous_fifo_uvm_verification synchronous_fifo_uvm_verification Public

   UVM verification environment for a synchronous FIFO including driver, monitor, scoreboard, coverage and multiple test scenarios.

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5. verilogproblems verilogproblems Public

   In this repository , it contain verilog problems

   Verilog

6. MBIST MBIST Public

   Memory Built-In Self-Test (MBIST) Architecture in Verilog

   Verilog 1