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fpu: implement Zfa minimum-number-or-NaN operations #298

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fpu: implement Zfa minimum-number-or-NaN operations #298

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8 changes: 4 additions & 4 deletions src/cpu/riscv_fpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -324,10 +324,10 @@ static slow_path void riscv_emulate_f_opc_op_impl(rvvm_hart_t* vm, const uint32_
riscv_emit_s(vm, rds, fpu_max32(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
return;
case 0x28002000UL: // fminm.s (Zfa)
riscv_write_s(vm, rds, fpu_min32(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
riscv_write_s(vm, rds, fpu_minm32(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
return;
case 0x28003000UL: // fmaxm.s (Zfa)
riscv_write_s(vm, rds, fpu_max32(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
riscv_write_s(vm, rds, fpu_maxm32(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
return;
case 0x2A000000UL: // fmin.d
riscv_emit_d(vm, rds, fpu_min64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
Expand All @@ -336,10 +336,10 @@ static slow_path void riscv_emulate_f_opc_op_impl(rvvm_hart_t* vm, const uint32_
riscv_emit_d(vm, rds, fpu_max64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
return;
case 0x2A002000UL: // fminm.d (Zfa)
riscv_write_d(vm, rds, fpu_min64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
riscv_write_d(vm, rds, fpu_minm64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
return;
case 0x2A003000UL: // fmaxm.d (Zfa)
riscv_write_d(vm, rds, fpu_max64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
riscv_write_d(vm, rds, fpu_maxm64(riscv_view_d(vm, rs1), riscv_view_d(vm, rs2)));
return;
case 0xA0000000UL: // fle.s
riscv_write_reg(vm, rds, fpu_is_fle32_sig(riscv_read_s(vm, rs1), riscv_read_s(vm, rs2)));
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44 changes: 44 additions & 0 deletions src/util/fpu_lib.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2001,4 +2001,48 @@ static forceinline fpu_f64_t fpu_max64(fpu_f64_t a, fpu_f64_t b)
#endif
}

static forceinline fpu_f32_t fpu_minm32(fpu_f32_t a, fpu_f32_t b)
{
if (fpu_is_nan32_soft(a) || fpu_is_nan32_soft(b)) {
if (fpu_is_snan32_soft(a) || fpu_is_snan32_soft(b)) {
fpu_raise_invalid();
}
return fpu_bit_u32_to_f32(FPU_LIB_FP32_CANONICAL_NAN);
}
return fpu_min32(a, b);
}

static forceinline fpu_f32_t fpu_maxm32(fpu_f32_t a, fpu_f32_t b)
{
if (fpu_is_nan32_soft(a) || fpu_is_nan32_soft(b)) {
if (fpu_is_snan32_soft(a) || fpu_is_snan32_soft(b)) {
fpu_raise_invalid();
}
return fpu_bit_u32_to_f32(FPU_LIB_FP32_CANONICAL_NAN);
}
return fpu_max32(a, b);
}

static forceinline fpu_f64_t fpu_minm64(fpu_f64_t a, fpu_f64_t b)
{
if (fpu_is_nan64_soft(a) || fpu_is_nan64_soft(b)) {
if (fpu_is_snan64_soft(a) || fpu_is_snan64_soft(b)) {
fpu_raise_invalid();
}
return fpu_bit_u64_to_f64(FPU_LIB_FP64_CANONICAL_NAN);
}
return fpu_min64(a, b);
}

static forceinline fpu_f64_t fpu_maxm64(fpu_f64_t a, fpu_f64_t b)
{
if (fpu_is_nan64_soft(a) || fpu_is_nan64_soft(b)) {
if (fpu_is_snan64_soft(a) || fpu_is_snan64_soft(b)) {
fpu_raise_invalid();
}
return fpu_bit_u64_to_f64(FPU_LIB_FP64_CANONICAL_NAN);
}
return fpu_max64(a, b);
}

#endif
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