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csr: validate CSRRS/CSRRC writes by register index #299

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csr: validate CSRRS/CSRRC writes by register index #299

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2 changes: 1 addition & 1 deletion src/core/rvvm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1161,7 +1161,7 @@ PUBLIC rvvm_hart_t* rvvm_create_user_thread(rvvm_machine_t* machine)
#if defined(USE_FPU)
// Initialize FPU by writing to status CSR
rvvm_uxlen_t mstatus = (FS_INITIAL << 13);
riscv_csr_op(thread, CSR_MSTATUS, &mstatus, CSR_SETBITS);
riscv_csr_op(thread, CSR_MSTATUS, &mstatus, CSR_SETBITS, true);
#endif

#if defined(USE_JIT)
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6 changes: 3 additions & 3 deletions src/cpu/riscv_csr.c
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Expand Up @@ -815,11 +815,11 @@ static forceinline bool riscv_csr_op_internal(rvvm_hart_t* vm, uint32_t csr_id,
return false;
}

bool riscv_csr_op(rvvm_hart_t* vm, uint32_t csr_id, rvvm_uxlen_t* dest, uint8_t op)
bool riscv_csr_op(rvvm_hart_t* vm, uint32_t csr_id, rvvm_uxlen_t* dest, uint8_t op, bool write)
{
if (riscv_csr_readonly(csr_id)) {
// This is a readonly CSR, only set/clear zero bits is allowed
if (unlikely(op == CSR_SWAP || *dest != 0)) {
// CSRRS/CSRRC with rs1/zimm = x0/0 are reads, not writes
if (unlikely(write)) {
return false;
}
}
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2 changes: 1 addition & 1 deletion src/cpu/riscv_csr.h
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Expand Up @@ -377,7 +377,7 @@ static forceinline bool riscv_csr_readonly(uint32_t csr_id)

// Perform a CSR operation, set *dest to original CSR value
// Returns false on failure (To raise exception afterwards)
bool riscv_csr_op(rvvm_hart_t* vm, uint32_t csr_id, rvvm_uxlen_t* dest, uint8_t op);
bool riscv_csr_op(rvvm_hart_t* vm, uint32_t csr_id, rvvm_uxlen_t* dest, uint8_t op, bool write);

// Initialize CSRs on a new hart
void riscv_csr_init(rvvm_hart_t* vm);
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12 changes: 6 additions & 6 deletions src/cpu/riscv_priv.c
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Expand Up @@ -145,23 +145,23 @@ slow_path void riscv_emulate_opc_system(rvvm_hart_t* vm, const uint32_t insn)
break;
case 0x01: { // csrrw
rvvm_uxlen_t val = vm->registers[rs1];
if (riscv_csr_op(vm, csr, &val, CSR_SWAP)) {
if (riscv_csr_op(vm, csr, &val, CSR_SWAP, true)) {
vm->registers[rds] = val;
return;
}
break;
}
case 0x02: { // csrrs
rvvm_uxlen_t val = vm->registers[rs1];
if (riscv_csr_op(vm, csr, &val, CSR_SETBITS)) {
if (riscv_csr_op(vm, csr, &val, CSR_SETBITS, rs1 != 0)) {
vm->registers[rds] = val;
return;
}
break;
}
case 0x03: { // csrrc
rvvm_uxlen_t val = vm->registers[rs1];
if (riscv_csr_op(vm, csr, &val, CSR_CLEARBITS)) {
if (riscv_csr_op(vm, csr, &val, CSR_CLEARBITS, rs1 != 0)) {
vm->registers[rds] = val;
return;
}
Expand All @@ -174,23 +174,23 @@ slow_path void riscv_emulate_opc_system(rvvm_hart_t* vm, const uint32_t insn)
break;
case 0x05: { // csrrwi
rvvm_uxlen_t val = bit_ext_u32(insn, 15, 5);
if (riscv_csr_op(vm, csr, &val, CSR_SWAP)) {
if (riscv_csr_op(vm, csr, &val, CSR_SWAP, true)) {
vm->registers[rds] = val;
return;
}
break;
}
case 0x06: { // csrrsi
rvvm_uxlen_t val = bit_ext_u32(insn, 15, 5);
if (riscv_csr_op(vm, csr, &val, CSR_SETBITS)) {
if (riscv_csr_op(vm, csr, &val, CSR_SETBITS, rs1 != 0)) {
vm->registers[rds] = val;
return;
}
break;
}
case 0x07: { // csrrci
rvvm_uxlen_t val = bit_ext_u32(insn, 15, 5);
if (riscv_csr_op(vm, csr, &val, CSR_CLEARBITS)) {
if (riscv_csr_op(vm, csr, &val, CSR_CLEARBITS, rs1 != 0)) {
vm->registers[rds] = val;
return;
}
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