[MasterLaplace]

What

cpu_context_switch(from, to) switches between two ring-0 contexts on one processor. It saves EBP, EBX, ESI, EDI, the stack pointer and the extended state.

• The policy for SIMD in ring 0, written on cpu_context_switch: every switch saves eagerly, never lazily through CR0.TS (LazyFP). A context that never touched its vector registers costs only the header.
• Each context names its save. extended_state_preferred_save takes the SDM's order: XSAVES, then XSAVEOPT, then XSAVE. FXSAVE is offered only while XCR0 enables nothing past SSE.
• cpu_context_prepare starts a context at its entry, from the initial state, on a 16-byte-aligned stack. An entry that returns is reported on COM1, then its processor halts.
• cpu_context_adopt makes the running code a context. It ends with an XRSTOR of empty mask, so any area may be adopted, even the one the processor last restored from.
• tools/instructions.sh --cpu names QEMU's processor model, so a budget can count the XSAVE path.
• First caller outside the tests: the tasks of Ring-0 tasks: a control block, task states and blocking waits #259.

Specification: said, says, because

#85's criterion said "a test preempts a task". It now says a context finds its registers after another context ran, because no task exists yet; preemption moves to #259.

Verify

./build.sh --server, then qemu-system-i386 -machine q35 -m 1G -smp 2 -kernel kernel/lpl.kernel -append lpl.test=context_switch.*, with -cpu max or -accel kvm -cpu host:

• Red before: registers lost and inherited, and under KVM the area adopted again kept its initial state.
• Server: q35 868/0, -cpu max 871/0 with 2 and 4 processors, KVM 871/0, pc 862/0, KVM pc with 4 processors 864/0. Satellite: -cpu max 721/0, KVM pc 714/0.
• Under KVM, integer contexts write no SSE or AVX byte with XSAVEOPT or XSAVES.
• 8 mutants, each failing under TCG or KVM: XSAVE for XSAVEOPT, no XRSTOR, FXSAVE only, no XCOMP_BV, no MXCSR, a misaligned frame, FXSAVE offered with AVX, no empty restore.
• context-switch.debug.budget: 58,852 instructions for 1,000 switches. Server tick unchanged.

Not in it

• ZMM and opmask registers are not probed: no machine at hand has AVX-512. Context switch with XSAVE and a ring-0 SIMD policy #85 stays open for that, and for its runs on real hardware.

Stacked on #805. Refs #85