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[None][feat] Enable MiniMax-M3 on Rubin (SM107): NVFP4 KV exemption and 128-token paged FMHA kernels - #20167
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WalkthroughThe pull request adds SM107 support for selected MiniMax-M3 sparse decode and FlashInfer TRTLLM-Gen paths. It updates 128-token draft-page routing and KV pool initialization, adjusts NVFP4 fallback behavior, and adds coverage for these paths and native MSA prefill. ChangesSM107 attention and MiniMax-M3 support
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~60 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant MiniMaxM3KVCacheManager
participant FlashInferTrtllmGenFmha
participant AttentionBackendSelector
MiniMaxM3KVCacheManager->>FlashInferTrtllmGenFmha: require route for extra page size
AttentionBackendSelector->>FlashInferTrtllmGenFmha: check backend order and environment
AttentionBackendSelector->>FlashInferTrtllmGenFmha: request support for page size
FlashInferTrtllmGenFmha-->>AttentionBackendSelector: handle configured extra page size or decline request
Possibly related PRs
Suggested reviewers: Merge Risk: 🔵 Low · up to
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| Check name | Status | Explanation | Resolution |
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| Docstring Coverage |  |
Docstring coverage is 50.91% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 110 functions across 23 files. (1 skipped… | Write docstrings for the functions missing them to satisfy the coverage threshold. |
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Check name Status Explanation Title check The title follows the required ticket and type format and clearly summarizes the main changes: MiniMax-M3 support on SM107, NVFP4 KV handling, and 128-token paged FMHA. Linked Issues check Check skipped because no linked issues were found for this pull request. Out of Scope Changes check Check skipped because no linked issues were found for this pull request. Description check The pull request description is complete and relevant. It explains the problem and solution, identifies the affected SM107 and MiniMax-M3 paths, provides detailed test coverage and results, and includ… Full details: Description check
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Explanation
The pull request description is complete and relevant. It explains the problem and solution, identifies the affected SM107 and MiniMax-M3 paths, provides detailed test coverage and results, and includes the repository checklist with the review confirmation checked.
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Full details: Docstring Coverage
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Explanation
Docstring coverage is 50.91% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 110 functions across 23 files. (1 skipped: 1 unsupported.)
Resolution
Write docstrings for the functions missing them to satisfy the coverage threshold.
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peihengh/m3-rubin-main-port-20261012
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@PerkzZheng, could you help to review this PR as trt-llm-torch-attention-devs? Thanks~ Assignment explanation
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@yuxianq, thanks for picking up this PR! I’ve handed off the trt-llm-torch-attention-devs review from @PerkzZheng to you. The 8 attention-review points now belong to @yuxianq; @PerkzZheng’s attention reservation has been released. Your review is already submitted, so the points count as completed work; no new review request was added. @PerkzZheng, no further attention review is requested from you. Thanks~ |
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Review comments at
@tests/unittest/_torch/attention/sparse/msa/test_msa_backend.py:
- Around line 2235-2239: Update the GPU equivalence test’s architecture gate to
allow only SM100 and SM103, matching the existing gate around line 1783; use
get_sm_version() rather than is_sm_100f() so unsupported SM10x devices skip
before running the packaged fmha_sm100 reference.
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⛔ Files ignored due to path filters: 1
examples/minimax_m3/rubin/msa_q8kv4_prefill_sm107.patch.gzis excluded by!**/*.gz
📒 Files selected for processing: 9
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.htensorrt_llm/_torch/attention/backends/fmha/msa_prefill.pytensorrt_llm/_torch/attention/backends/sparse/minimax_m3/kernels/msa_utils.pytensorrt_llm/_torch/attention/backends/sparse/minimax_m3/kernels/triton_sparse_decode.pytensorrt_llm/_torch/attention/backends/sparse/minimax_m3/msa_backend.pytensorrt_llm/_torch/pyexecutor/model_loader.pytests/unittest/_torch/attention/sparse/msa/test_msa_backend.pytests/unittest/_torch/attention/test_context_fmha_kernel_presence.pytests/unittest/_torch/test_model_config.py
🚧 Files skipped from review as they are similar to previous changes: 1
- tensorrt_llm/_torch/attention/backends/sparse/minimax_m3/kernels/triton_sparse_decode.py
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Brings the branch up to main 6cb5a79. One test-only conflict in tests/unittest/_torch/attention/test_flashinfer_trtllm_gen_fmha.py: main's FP8 custom-mask assertion (NVIDIA#20387) is kept, and the NVIDIA#20676 cherry-pick's SM107 tests (test_flashinfer_availability_by_sm, test_sm107_serves_only_extra_page_sizes) are kept after it. NVIDIA#20676 is on release/1.3, not main, so they are not duplicates. Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
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PR_Github #79977 [ run ] triggered by Bot. Commit: |
… zero the KV pools Review follow-ups for the Rubin (SM107) MiniMax-M3 enablement: - Zero the MiniMax-M3 KV pools at allocation unconditionally; drop the TRTLLM_M3_KV_POOL_ZERO_INIT switch. - On SM107, the P128 setup check now only requires flashinfer_trtllm_gen to be enabled in TLLM_FMHA_LIBS: its 128-token-page cubins ship with it. - The model keeps SDPA for its dense layers by checking SM107 directly. - The NVFP4 KV exemption reuses is_minimax_m3(). - Run the SM107 P128 FlashInfer oracle in the GR100 post-merge stage, tighten a KeyError assertion and fix a list paragraph in the deployment guide. Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
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PR_Github #80057 [ run ] triggered by Bot. Commit: |
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PR_Github #79977 [ run ] completed with state |
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Automatically added "ci: full pre-merge approved" because this PR has satisfied the required GitHub review approvals. Unresolved review conversations and other required checks remain independent merge requirements. |
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PR_Github #80057 [ run ] completed with state
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PR_Github #80149 [ run ] triggered by Bot. Commit: |
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PR_Github #80149 [ run ] completed with state |
Dev Engineer Review
FallbackFmha.#20629.QA Engineer Review
Per-File QA Perspective
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h: Selects NVRTC for supported SM107 128-token paged FMHA cases. Verify dtype and output conditions.tensorrt_llm/_torch/attention/backends/sparse/minimax_m3/kernels/triton_sparse_decode.py: Enables SM107 NVFP4 sparse decode. Verify kernel compatibility.tensorrt_llm/_torch/pyexecutor/model_loader.py: Preserves MiniMax-M3 MSA NVFP4 KV caches on SM107. Verify other configurations still use the FP8 fallback.tensorrt_llm/_torch/attention/backends/fmha/fallback.py: Allows 128-token paged prefill on SM107. Verify other architectures remain rejected.tensorrt_llm/_torch/attention/sparse/minimax_m3/cache_manager.py: Zero-initializes KV-pool views by default. Verify the environment override and initialization cost.tests/unittest/_torch/attention/sparse/msa/test_minimax_m3_sparse_attn_decode.py: Tests SM107 NVFP4 policy behavior. Test-list registration is not confirmed.tests/unittest/_torch/attention/sparse/msa/test_msa_backend.py: Tests MSA cache handling, validation, mapping, and dispatch. Test-list registration is not confirmed.tests/unittest/_torch/attention/test_context_fmha_kernel_presence.py: Tests SM107 runtime-generated FMHA kernel availability. Test-list registration is not confirmed.tests/unittest/_torch/test_model_config.py: Tests SM107 KV-cache quantization propagation. Test-list registration is not confirmed.tests/unittest/_torch/attention/test_fallback_fmha_extra_page_sizes.py: Tests architecture-specific paged-prefill admission and cached contexts. Test-list registration is not confirmed.tests/unittest/_torch/attention/sparse/msa/test_minimax_m3_kv_pool_zero_init.py: Tests zero initialization for MiniMax-M3 KV pools. Test-list registration is not confirmed.Description
MiniMax-M3 with an NVFP4 or FP8 KV cache does not serve on Rubin (sm_107) on main today: the NVFP4 cache is downgraded to FP8, the NVFP4 sparse decode rejects the device, and with Eagle3 the draft layers need paged FMHA at M3's 128-token pages. This PR adds:
validate_and_set_kv_cache_quantskips MiniMax-M3 MSA. Its sparse layers keep NVFP4 and its dense and draft layers stay FP8. Every other configuration still falls back to FP8.{128}extra page size on sm_107.TLLM_FMHA_LIBSexcludesflashinfer_trtllm_gen, instead of failing at the first prefill. Configurations whose layers all stay on SDPA are not affected.FallbackFmhasm_107 admission are removed.fmhaKernels.h,fallback.pyand the kernel-presence test are back to main.The deployment guide lists the Sm107a 128-token-page cubins and how to pre-populate
FLASHINFER_CUBIN_DIRfor offline nodes (FLASHINFER_NO_DOWNLOAD=1).Native MSA prefill and the Rubin context-path optimizations are in #20629.
Test Coverage
All on Rubin (sm_107), built from source for
107-real, MiniMax-M3 NVFP4 at TP2 with the Eagle3 drafter:test_flashinfer_trtllm_gen_sm107_p128.pyoracle: FlashInfer vs an FP32 reference at M3's 16:1 heads, for cached-prefix / chunked / generation / verify / mixed batches, with zero and NaN page tails. Tolerances come from a 16-seed sweep. It asserts FlashInfer served each call.test_minimax_m3_shared_draft_layers.py.FLASHINFER_NO_DOWNLOAD=1and a pre-populatedFLASHINFER_CUBIN_DIR. An offlinetrtllm-serverun fetched 0 cubins.trtllm-servewith the NVFP4 KV cache and Eagle3: no tracebacks, the draft's 128-token-page steps served by FlashInfer, 0 fallback.PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
If PR introduces API changes, an appropriate PR label is added - either
api-compatibleorapi-breaking. Forapi-breaking, includeBREAKINGin the PR title.Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
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