[TRTLLM-17096][feat] modeling_v2: GLM-5.2 NVFP4 low-latency decode target for GB300

cpp/tensorrt_llm/CMakeLists.txt

@@ -199,6 +199,7 @@ set(TRTLLM_LINK_LIBS
     mamba2_mtp_ssm_cache_src
     kda_decode_src
     kimi_k3_attn_res_src
+    glm_moe_dsa_kernels_src
     kimi_k3_model_src
     ws_layernorm_src
     fusedGatedRMSNormQuant_src

cpp/tensorrt_llm/kernels/CMakeLists.txt

@@ -32,6 +32,7 @@ add_subdirectory(fusedGatedRMSNormQuant)
 add_subdirectory(mamba2MTPSSMCache)
 add_subdirectory(kdaDecode)
 add_subdirectory(kimiK3AttnRes)
+add_subdirectory(glmMoeDsa)
 add_subdirectory(mhcKernels)
 add_subdirectory(compressorKernels)
 add_subdirectory(fusedSampling)
@@ -78,6 +79,15 @@ list(FILTER SRC_CPP EXCLUDE REGEX "kdaDecode/.*")
 list(FILTER SRC_CU EXCLUDE REGEX "kdaDecode/.*")
 list(FILTER SRC_CPP EXCLUDE REGEX "kimiK3AttnRes/.*")
 list(FILTER SRC_CU EXCLUDE REGEX "kimiK3AttnRes/.*")
+# The GLM-5.2 GB300 target's kernels build in glmMoeDsa/'s own library; the
+# other glmMoeDsa/ kernels stay in this glob.
+list(
+  FILTER
+  SRC_CU
+  EXCLUDE
+  REGEX
+  "glmMoeDsa/(crossRankTopk|crossRankTopkClusterMerge|crossRankTopkGlobalEmit|denseMlp|draftLiveRowHop|draftRoutedMoe|draftTail|indexerLayerRopeKvAppend|postAttentionHop|postAttentionHopFromPartials|postAttentionHopRouting|ropeKvAppend|sparseMlaDecode)\\.cu$"
+)
 list(FILTER SRC_CPP EXCLUDE REGEX "mhcKernels/.*")
 list(FILTER SRC_CU EXCLUDE REGEX "mhcKernels/.*")
 list(FILTER SRC_CPP EXCLUDE REGEX "compressorKernels/.*")

cpp/tensorrt_llm/kernels/glmMoeDsa/CMakeLists.txt

@@ -0,0 +1,42 @@
+# SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES.
+# All rights reserved. SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+
+add_library(
+  glm_moe_dsa_kernels_src OBJECT
+  crossRankTopk.cu
+  crossRankTopkClusterMerge.cu
+  crossRankTopkGlobalEmit.cu
+  denseMlp.cu
+  draftLiveRowHop.cu
+  draftRoutedMoe.cu
+  draftTail.cu
+  indexerLayerRopeKvAppend.cu
+  postAttentionHop.cu
+  postAttentionHopFromPartials.cu
+  postAttentionHopRouting.cu
+  ropeKvAppend.cu
+  sparseMlaDecode.cu)
+
+# The GLM-MoE-DSA kernels are written for the SM100 (datacenter Blackwell)
+# family (for example 32-byte global loads), so pin the target to that family
+# instead of inheriting the global architecture list. On builds without any
+# sm_100-family architecture the target still compiles: device code that needs
+# newer instructions is guarded by __CUDA_ARCH__ and traps.
+set_cuda_architectures(glm_moe_dsa_kernels_src 100f)
+
+set_property(TARGET glm_moe_dsa_kernels_src PROPERTY POSITION_INDEPENDENT_CODE
+                                                     ON)
+set_property(TARGET glm_moe_dsa_kernels_src PROPERTY CUDA_RESOLVE_DEVICE_SYMBOLS
+                                                     ON)