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BPU: sample BTB ready on lookup, not every cycle #284

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poemonsense merged 1 commit into from
Sep 20, 2026
Merged

BPU: sample BTB ready on lookup, not every cycle #284

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4 changes: 2 additions & 2 deletions src/main/scala/nutcore/frontend/BPU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ class BPU_ooo extends NutCoreModule {
// we should latch the input pc for one cycle
val pcLatch = RegEnable(io.in.pc.bits, io.in.pc.valid)
val btbHit = Wire(Vec(4, Bool()))
(0 to 3).map(i => btbHit(i) := btbRead(i).valid && btbRead(i).tag === btbAddr.getTag(pcLatch) && !flush && RegNext(btb(i).io.r.req.ready, init = false.B))
(0 to 3).map(i => btbHit(i) := btbRead(i).valid && btbRead(i).tag === btbAddr.getTag(pcLatch) && !flush && RegEnable(btb(i).io.r.req.ready, false.B, io.in.pc.valid))
// btbHit will ignore pc(2,0). pc(2,0) is used to build brIdx
val crosslineJump = btbRead(3).crosslineJump && btbHit(3) && !io.brIdx(0) && !io.brIdx(1) && !io.brIdx(2)
io.crosslineJump := crosslineJump
Expand Down Expand Up @@ -317,7 +317,7 @@ class BPU_inorder extends NutCoreModule {
// since there is one cycle latency to read SyncReadMem,
// we should latch the input pc for one cycle
val pcLatch = RegEnable(io.in.pc.bits, io.in.pc.valid)
val btbHit = btbRead.valid && btbRead.tag === btbAddr.getTag(pcLatch) && !flush && RegNext(btb.io.r.req.ready, init = false.B) && !(pcLatch(1) && btbRead.brIdx(0))
val btbHit = btbRead.valid && btbRead.tag === btbAddr.getTag(pcLatch) && !flush && RegEnable(btb.io.r.req.ready, false.B, io.in.pc.valid) && !(pcLatch(1) && btbRead.brIdx(0))
// btb.io.r.req.ready is used to indicate whether BTB SRAM is doing reset (if is true.B, btbRead.valid can be fake)
// we don't use btb.io.r.req.fire because of btb.io.r.req.valid only last for 1 cycle, further causes fake BTB miss
// See https://github.com/OSCPU/NutShell/pull/147
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