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The gfx1250 A8W8 and A8W4 GEMMs accepted tile_k below the 128-deep FP8 WMMA and warp tiles below 16 rows or columns. Those kernels issue no WMMA and store zeros. Raise ValueError for them, with the check and message of gemm_bf16_gfx1250. Signed-off-by: Jin Pan <jin.pan@amd.com>
launch_gemm_a8w8 requires N % tile_n == 0, K % tile_k == 0 and K // tile_k >= num_buffers - 1 (blockscale also N % 128 == 0); its docstring now says so. For a padded C, _run_and_check fills the columns past N with a signaling-NaN bit pattern and checks that they keep it, so any store past N fails the test, a NaN store included. Folded in from #1229. Signed-off-by: Jin Pan <jin.pan@amd.com>
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On gfx1250,
launch_gemm_a8w8andlaunch_gemm_a8w4_mxscaleaccepted atile_kbelow the 128-deep FP8 WMMA, and a warp tile below 16 rows or columns. Such a kernel issues no WMMA and stores zeros without an error. On FP8 per-token 9728 x 8192 x 8192, for example,t256x256x64returned an all-zero C.Both kernels now raise
ValueErrorfor these tiles before anything is built, with the check and message ofgemm_bf16_gfx1250:tile_ka multiple of 128,tile_ma multiple of16 * m_warp,tile_na multiple of16 * n_warp. No existing test case or smoke config changes.This PR also carries #1229, the shape side of the same contract. The
launch_gemm_a8w8docstring states the shapes it accepts:N % tile_n == 0,K % tile_k == 0andK // tile_k >= num_buffers - 1(blockscale alsoN % 128 == 0); a partial last M tile is clamped. For the cases with a padded C (ldc > N),_run_and_checkfills the columns past N with a signaling-NaN bit pattern before the launch and checks that the bits do not change, so a store past N fails the test, even one that stores a NaN.test_gemm_rejects_tiles_off_the_wmma_shapecovers the A8W4, per-token and blockscale modes. Against main's kernels it fails withDID NOT RAISE. On a gfx1250 part,test_gemm_fp8fp4_gfx1250.pypasses (126 tests) with both changes; CI skips these tests on its runners.