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[Bugfix][gfx1250] Reject FP8 and A8W4 GEMM tiles that issue no WMMA, and test that stores stay inside N - #1264

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fix/gfx1250-fp8-tile-check
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jhinpan wants to merge 2 commits into
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fix/gfx1250-fp8-tile-check

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@jhinpan

@jhinpan jhinpan commented Oct 11, 2026 •

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On gfx1250, launch_gemm_a8w8 and launch_gemm_a8w4_mxscale accepted a tile_k below the 128-deep FP8 WMMA, and a warp tile below 16 rows or columns. Such a kernel issues no WMMA and stores zeros without an error. On FP8 per-token 9728 x 8192 x 8192, for example, t256x256x64 returned an all-zero C.

Both kernels now raise ValueError for these tiles before anything is built, with the check and message of gemm_bf16_gfx1250: tile_k a multiple of 128, tile_m a multiple of 16 * m_warp, tile_n a multiple of 16 * n_warp. No existing test case or smoke config changes.

This PR also carries #1229, the shape side of the same contract. The launch_gemm_a8w8 docstring states the shapes it accepts: N % tile_n == 0, K % tile_k == 0 and K // tile_k >= num_buffers - 1 (blockscale also N % 128 == 0); a partial last M tile is clamped. For the cases with a padded C (ldc > N), _run_and_check fills the columns past N with a signaling-NaN bit pattern before the launch and checks that the bits do not change, so a store past N fails the test, even one that stores a NaN.

test_gemm_rejects_tiles_off_the_wmma_shape covers the A8W4, per-token and blockscale modes. Against main's kernels it fails with DID NOT RAISE. On a gfx1250 part, test_gemm_fp8fp4_gfx1250.py passes (126 tests) with both changes; CI skips these tests on its runners.

The gfx1250 A8W8 and A8W4 GEMMs accepted tile_k below the 128-deep FP8
WMMA and warp tiles below 16 rows or columns. Those kernels issue no
WMMA and store zeros. Raise ValueError for them, with the check and
message of gemm_bf16_gfx1250.

Signed-off-by: Jin Pan <jin.pan@amd.com>
launch_gemm_a8w8 requires N % tile_n == 0, K % tile_k == 0 and
K // tile_k >= num_buffers - 1 (blockscale also N % 128 == 0); its
docstring now says so. For a padded C, _run_and_check fills the columns
past N with a signaling-NaN bit pattern and checks that they keep it, so
any store past N fails the test, a NaN store included.

Folded in from #1229.

Signed-off-by: Jin Pan <jin.pan@amd.com>
@jhinpan jhinpan changed the title [Bugfix][gfx1250] Reject FP8 and A8W4 GEMM tiles that issue no WMMA [Bugfix][gfx1250] Reject FP8 and A8W4 GEMM tiles that issue no WMMA, and test that stores stay inside N Oct 13, 2026
@jhinpan
jhinpan requested review from aoli26 and zhiding512 October 13, 2026 20:43

@aoli26 aoli26 left a comment

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LGTM

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2 participants