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[llvm] Bump LLVM hash and add gfx1250-strict support - #1289
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jli-melchior wants to merge 15 commits into
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Update LLVM to 659323446eff (includes all gfx1250-strict patches up to
WMMA latency modeling) and fix build compatibility with the new MLIR:
- Opt out of strict properties in assembly format for Fly/FlyROCDL/FlyKtrace dialects
- Adapt to llvm::make_scope_exit -> llvm::scope_exit rename
- Adapt to gpu::LaunchFuncOp::create unified signature
Add gfx1250-strict as a recognized target:
- Add SMEM capacity entry for gfx1250-strict (same 320KB LDS)
- Change test arch guards from exact == "gfx1250" to startswith("gfx1250")
- Update arch_compat glob to "gfx1250*"
Co-Authored-By: Claude <noreply@anthropic.com>
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The LLVM bump (659323446eff) replaced the boolean `wave64` pass option with an unsigned `wavesize` option (32 or 64). Pass `get_warp_size(chip)` directly instead of converting to a bool string. Co-Authored-By: Claude <noreply@anthropic.com>
…rom_attr The LLVM bump changed how MLIR enum attributes are printed: the Fly address_space attribute now prints as `#fly.address_space<global>` instead of the old `#fly<address_space global>`. Match both formats so make_buffer_ptr and other callers correctly recognize global-space pointers. Co-Authored-By: Claude <noreply@anthropic.com>
The upstream LLVM MLIR changed dialect attribute printing from the
legacy `#dialect<attr_name value>` format to the standard
`#dialect.attr_name<value>` format. Update all affected attribute
parse strings:
- address_space_from_attr: add `#fly.address_space<...>` matching
- sched_group_mask: `#rocdl.sched_group_mask<...>`
- mfma_perm_b: `#rocdl.mfma_perm_b<...>`
- wmma attrs: `#rocdl.{attr_name}<...>`
Co-Authored-By: Claude <noreply@anthropic.com>
The new MLIR prints address spaces as #fly.address_space<shared> but older .mlir test files use bare keywords (shared, global, register). Add a parseOptionalKeyword fallback in parseAddressSpaceAttribute so both formats are accepted. Co-Authored-By: Claude <noreply@anthropic.com>
The custom LLVM now prints enum-like memory space keywords wrapped in angle brackets (e.g. <register>, <shared>, <generic>, <global>). Update test assertions and ir.Type.parse() calls to match. Co-Authored-By: Claude <noreply@anthropic.com>
Replace legacy #fly<atomic_op add> with #fly.atomic_op<add> in test files to match the standard MLIR attribute print format. Co-Authored-By: Claude <noreply@anthropic.com>
The type printer now emits `fly.ptr<i8, #fly.address_space<global>>` instead of `fly.ptr<i8, global>`. Co-Authored-By: Claude <noreply@anthropic.com>
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The type printer now emits address-space keywords wrapped in angle brackets (e.g. <global>, <shared>, <register>) inside fly.ptr and fly.memref types. Update all CHECK-line assertions to match. Input MLIR lines are left with bare keywords since the C++ parser backward-compat fix (718f18b) accepts both formats. Co-Authored-By: Claude <noreply@anthropic.com>
The LLVM bump removed the `lsr-drop-solution` cl::opt. Instead of crashing, log a warning and skip unknown options — these are tuning hints, not correctness requirements. Kernel compile_hints should not need to track internal LLVM option removals. Co-Authored-By: Claude <noreply@anthropic.com>
The patch context drifted (new kBarrierAddressSpace constant, shifted line numbers) against the 659323446eff pin. Content is unchanged; only hunk offsets and index hashes are updated. Co-Authored-By: Claude <noreply@anthropic.com>
…tests
The backward-compat keyword parser in parseAddressSpaceAttribute never
worked: parseOptionalAttribute greedily consumed bare keywords (global,
shared, register) before the fallback parseOptionalKeyword path could
run. Fix by trying parseOptionalLess first (handles the current <kw>
print format), then bare keyword, then dialect-qualified attributes.
Update remaining FileCheck tests for the new upstream MLIR print format:
- {alignment = N : i64} → <alignment = N> (llvm.load/store properties)
- {offsets = [...], ...} → offsets = [...], ... (vector strided slice)
- {signA = true, ...} → <signA = true, ...> (rocdl.wmma properties)
- bare enum keywords → <keyword> (address space, mma operand id)
- attribute print order: signA, signB, clamp (alphabetical)
Co-Authored-By: Claude <noreply@anthropic.com>
Co-Authored-By: Claude <noreply@anthropic.com>
Inline asm hid ds_read_b64_tr_b16/tr_b8 from the waitcnt inserter, so the dualwave kernel consumed V before the LDS load completed. Co-authored-by: Cursor <cursoragent@cursor.com>
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Update LLVM to 659323446eff (includes all gfx1250-strict patches up to WMMA latency modeling) and fix build compatibility with the new MLIR:
Add gfx1250-strict as a recognized target:
Motivation
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Test Plan
Test Result
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