[AMD] MiniMax-M3 FP4/FP8 MI355X ATOMESH (disagg): (0701) refactor config

[seungrokj]

Summary

• Refactor server_atom.sh and models_atom.yaml to centralize model-specific ATOM config (block size, memory fraction, model length, quant config, hf overrides) and support per-role (prefill/decode) flags for TP+DPA, EP+DPA, and online_quant_config
• Move hardcoded server tuning params from launch scripts into models_atom.yaml with env-var override support
• Add minimaxm3-fp4/fp8-mi355x-atom-disagg-mtp recipes to amd-master.yaml for EAGLE3 speculative decoding (DECODE_MTP_SIZE=3)
• Remove redundant SPEC_DECODING gating; use MODEL_MTP_FLAGS + DECODE_MTP_SIZE > 0 directly
• Split online_quant_config into DPA and non-DPA variants (FP8 uses different exclude patterns with DPA)

PR Review Checklist

• Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
• Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
• Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this.
• Verified that this PR passes evals. Please link to GitHub Action workflow that shows this.
• Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
• If a company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
• Verified that the single-node recipes are similar to the official vLLM recipes and/or the SGLang cookbook:
  • If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
• If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

🤖 Generated with Claude Code

中文说明

重构 server_atom.sh 和 models_atom.yaml，将模型特定的 ATOM 配置（block size、内存比例、模型长度、量化配置、hf overrides）集中管理，支持按角色（prefill/decode）分别设置 TP+DPA、EP+DPA 和 online_quant_config 参数。将启动脚本中的硬编码调优参数迁移到 models_atom.yaml，支持环境变量覆盖。新增 minimaxm3-fp4/fp8-mi355x-atom-disagg-mtp 配置到 amd-master.yaml，支持 EAGLE3 投机解码（DECODE_MTP_SIZE=3）。移除冗余的 SPEC_DECODING 判断，改用 MODEL_MTP_FLAGS + DECODE_MTP_SIZE > 0 直接控制。将 online_quant_config 拆分为 DPA 和非 DPA 两个变体（FP8 在 DPA 模式下使用不同的 exclude pattern）。

한국어 설명

server_atom.sh와 models_atom.yaml을 리팩토링하여 모델별 ATOM 설정(block size, 메모리 비율, 모델 길이, 양자화 설정, hf overrides)을 중앙 집중화하고, 역할별(prefill/decode) TP+DPA, EP+DPA, online_quant_config 플래그를 지원합니다. 런치 스크립트의 하드코딩된 서버 튜닝 파라미터를 models_atom.yaml로 이전하고 환경 변수 오버라이드를 지원합니다. amd-master.yaml에 minimaxm3-fp4/fp8-mi355x-atom-disagg-mtp 레시피를 추가하여 EAGLE3 투기적 디코딩(DECODE_MTP_SIZE=3)을 지원합니다. 불필요한 SPEC_DECODING 게이팅을 제거하고 MODEL_MTP_FLAGS + DECODE_MTP_SIZE > 0으로 직접 제어합니다. online_quant_config를 DPA/비-DPA 변형으로 분리합니다 (FP8은 DPA 모드에서 다른 exclude 패턴 사용).

[github-actions]

Thanks for the contribution! For vLLM & SGLang, please ensure that your recipes is similar to the official vLLM recipes and/or the SGLang cookbook

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---

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[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28694482428
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28694482428

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28744563585
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28744563585

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28760615939
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28760615939

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28760615939
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28760615939

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28761586977
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28761586977

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28761627583
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28761627583

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28761627583
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28761627583

[seungrokj]

@chunfangamd @billishyahao can you plz review this
recipe is at ROCm/ATOM#1447

[seungrokj]

/reuse-sweep-run

[billishyahao]

As a PR reviewer and CODEOWNER, I have reviewed this and have:

• Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
• Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
• Verified that this PR has passed PR validation. https://inferencex.semianalysis.com/inference?unofficialRun=28761627583.
• Verified that this PR passes evals. https://inferencex.semianalysis.com/evaluation?unofficialRun=28761627583.
• Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
• Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
• If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
• If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
• Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
  • If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
• If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

• insert any additional info here

Signed: billishyahao

[Klaud-Cold]

❌❌❌ REJECTED ❌❌❌

@billishyahao — blocking issue: the sign-off uses a stale/abridged copy of the checklist. Three items from the current PR_REVIEW_CHECKLIST.md are missing entirely (spec-decoding chat templates; no benchmark hacks / no --hf-overrides reducing model-architecture FLOPs; upstream vLLM/SGLang Docker images), and the "Single-node recipes" item is left unchecked with no explanation in an additional detail section. Please re-post the sign-off using the full current template (the missing items would all check out — see rows below).

✅ Check 0 (CODEOWNER): PASS — billishyahao owns configs/amd-master.yaml (specific CODEOWNERS line); remaining paths are catch-all.
✅ Check 1 (Sweep on in-PR commit): PASS — commit e1f3943 (in PR) has green executed multi-node 1k1k/8k1k / + multi-node eval / jobs: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/28761627583 (single-node jobs correctly skipped — multi-node-only PR).
✅ Check 2 (Evals pass): PASS — GSM8K em_strict 0.9424/0.9424 (FP4) and 0.9530/0.9416 (FP8) across all 4 lanes, n=1319, on image rocm/atom-dev:nightly_202607011530 matching this PR's config.
➖ Check 3 (Recipe link): N/A — disaggregated/multi-node submission (benchmarks/multi_node/**, multinode: true, disagg: true); the recipe-link requirement applies to single-node recipes only.
✅ Check 4 (Reuse command): PASS — /reuse-sweep-run posted by seungrokj (COLLABORATOR).
❌ Check 5 (Latest checklist template): FAIL — sign-off is missing 3 current-template items (spec-decode chat templates; benchmark-hacks/--hf-overrides FLOPs rule; upstream vLLM/SGLang Docker images) and leaves "Single-node recipes similar to official recipes" unchecked with no additional-detail explanation.
✅ Check 6 (Upstream images / engine-first): PASS — changed entries are framework: atom-disagg (upstream-image rule targets vLLM/SGLang entries); vLLM submissions for minimaxm3 on MI355X already exist (minimaxm3-fp8-mi355x-vllm, minimaxm3-fp4-mi355x-vllm).
✅ Check 7 (No architecture hacks): PASS — PR removes the DeepSeek-V4-Pro --hf-overrides index-cache hack and adds none; online_quant_config (ptpc_fp8 with exclude layers) is a precision change backed by passing evals.
✅ Check 8 (Spec-decode chat template): PASS — all added config lanes set DECODE_MTP_SIZE=0, and amd_utils/bench.sh adds --use-chat-template whenever IS_MTP=true.

[Klaud-Cold]

✅✅✅ Verdict: PASS ✅✅✅

Supersedes the earlier REJECTED verdict for this SHA: the sign-off body now contains the full current checklist template, and all checks verify independently.

✅ Check 0 (CODEOWNER): PASS — billishyahao is a listed owner of configs/amd-master.yaml (specific CODEOWNERS line); the remaining changed paths are catch-all-only and covered.
✅ Check 1 (Sweep on in-PR commit): PASS — commit e1f3943 (in this PR) has green executed multi-node 1k1k/8k1k / and multi-node eval / jobs: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/28761627583 (single-node jobs correctly skipped — multi-node-only PR).
✅ Check 2 (Evals pass): PASS — GSM8K em_strict 0.9424/0.9424 (FP4) and 0.9530/0.9416 (FP8) across all 4 lanes, n=1319, run on rocm/atom-dev:nightly_202607011530 matching this PR's config image.
➖ Check 3 (Recipe link): N/A — disaggregated/multi-node submission (benchmarks/multi_node/**, framework: atom-disagg, multinode: true, disagg: true); the recipe-link requirement applies to single-node recipes only.
✅ Check 4 (Reuse command): PASS — /reuse-sweep-run posted by seungrokj (COLLABORATOR).
✅ Check 5 (Latest checklist template): PASS — all 9 current-template items present and checked in the sign-off; the final conditional item is unchecked and vacuous since every criterion above it is affirmed.
✅ Check 6 (Upstream images / engine-first): PASS — changed entries are framework: atom-disagg (upstream-image rule targets vLLM/SGLang entries); vLLM submissions for this model+SKU already exist (minimaxm3-fp8-mi355x-vllm, minimaxm3-fp4-mi355x-vllm).
✅ Check 7 (No architecture hacks): PASS — the PR removes the DeepSeek-V4-Pro --hf-overrides index-cache override and adds none; online_quant_config (ptpc_fp8 with excluded layers) is a precision change backed by the passing evals above.
✅ Check 8 (Spec-decode chat template): PASS — all added lanes set DECODE_MTP_SIZE=0 (spec decoding inactive; evals confirm spec_decoding: none), and when MTP is enabled server_atom.sh sets IS_MTP=true, which makes amd_utils/bench.sh pass --use-chat-template.

[seungrokj]

@functionstackx @Oseltamivir can you plz merge this ?