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kcaisley
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Sep 30, 2026
kcaisley
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- Add and refine standalone Xilinx behavioral models, including DDR reset/set and inversion behavior.
- Apply HDL formatting and lint fixes; share pyproject.toml configuration between local hooks and separate CI jobs.
- Use Ruff for Python formatting/import sorting and include laboratory instrument driver updates.
- Fix command-sequencer capture alignment and document remaining model limitations.
- Checked 195 primitive tests, DDR/buffer comparisons with AMD models, the failing sequencer test with both ODDR implementations, and Verible/Verilator/Slang checks.
- Add and refine standalone Xilinx primitive models with interface and behavior checks. - Apply automated HDL formatting and remaining Verilog-2005 lint fixes. - Centralize HDL configuration in pyproject.toml with shared tool scripts and separate CI jobs. - Use Ruff for Python formatting and import sorting; extend laboratory instrument controls. - Verify primitive tests against AMD models and fix command-sequencer capture alignment.
- Complete delay, clock and serializer parameter behavior and add focused simulation checks. - Remove nettype directives and obsolete include fragments; align module filenames and references. - Check functional behavior with Icarus and enforce Verilog-2005 with the HDL linters.
- Replace tracked Vivado and ISE projects with per-example Makefiles and Tcl scripts. - Put generated projects, reports and bitstreams under build/fpga. - Preserve source lists, devices and constraints; verify four projects with the installed vendor tools.
- Use four matching check names with comments explaining their complementary coverage. - Reduce tools to run.py, sources.py and install.sh; read shared settings from sources.hdl. - Download pinned native binaries and use pyslang wheels, with CI caches and build output directories. - Remove the pytest fixture override and verify all hooks, 382 Icarus cases and seven Verilator cases.
- Describe missing case defaults and source conventions checked by Verible. - Keep the hook and CI explanations aligned.
- Store Icarus and Verilator outputs in separate build/sim directories. - Reject overlapping POSIX socket-test runners and reap simulator processes. - Add regression checks for output paths and concurrent-run protection.
- Apply the same interface and functional assertions to Basil and AMD models. - Use valid serializer modes and allow documented pipeline settling. - Require PLL reset after reference-clock loss and remove Basil-only assertions.
- Run Icarus on Python 3.10-3.14 and report Verilator separately. - Collect coverage once and simplify runner names and reporting. - Update Ruff while retaining the existing lint rules and add cleanup TODOs. - Simplify shared tool installation and move documentation outputs under build.
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This pull request is a draft because it is far too large to be reviewed in a single go. My plan is to get the whole thing working, then squash it down and manually break it apart into a dozen or so smaller pull requests when the time comes :) |
- Replace generated Makefiles with runner-based background simulations. - Merge primitive stimulus and launch code and rename family tests to 7series. - Replace primitive configuration environment variables with per-run JSON. - Build directly in simulator-specific directories and check output placement. - Remove cocotb-test and update simulation documentation.
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- Create the configured basetemp parent for clean local and CI runs. - Check compilation failures using the runner's CalledProcessError. - Verify all 73 affected primitive and runner regression tests.
- Accept the compiler failure exception forms used by Cocotb 2.0 and 2.1. - Check diagnostic text and preserve failed-build cleanup assertions. - Verify runner tests on both versions and all 368 tests on Cocotb 2.1.
cbespin
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Oct 8, 2026
cbespin
reviewed
Oct 28, 2026
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| module ODDR ( | ||
| input wire D1, D2, | ||
| input wire C, CE, R, S, | ||
| input wire D1, | ||
| D2, | ||
| input wire C, | ||
| CE, | ||
| R, | ||
| S, |
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Not sure if I am a fan of that :/
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