Just a curious enthusiastic explorer
✧/ᐠ - ꞈ - ᐟ\
Highlights
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From_Verilog_To_TLV
From_Verilog_To_TLV PublicRamping up on own by converting Verilog example codes from H&H book into TLV 😌 Yes, I like suffering.
TL-Verilog
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silly-tapeout
silly-tapeout PublicAn Open-Source silicon project to get my first ever silly chip.
Verilog 1
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