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refactor(simd): share quantizer, reduction, rescale-search and dispatch boilerplate - #191
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The AVX2, AVX-512 and NEON uint8 and uint16 scalar quantizers repeated the zero-range fill, reciprocal setup and scalar tail, differing only in the final narrowing and store. Each backend now has one template over the code type.
Three translation-unit copies of the same tree reduction become one internal-linkage helper. It replaces an external-linkage inline copy in an AVX2 translation unit. The generated kernels are unchanged.
The AVX2 and AVX-512 evaluators repeated the exact event-scale recovery and scalar tail, and four wrappers repeated the -1 fallback convention. Both now live in rescale_search.hpp with internal linkage.
transfer_lut_hacc_avx2 used no vector instructions and wrote the same Pair32 layout as transfer_lut_hacc_generic, which the NEON backend already uses. The outputs are byte-identical.
Thirteen dispatch wrappers repeated an #if block choosing resolve_optional_kernel on ARM64 or RABITQ_RESOLVE elsewhere, with inconsistent ARM64 guards. RABITQ_RESOLVE_NEON keeps each target referencing only its own ISA's symbols; the x86 dispatch code is unchanged.
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Summary
Remove duplicated non-kernel logic around the SIMD backends. Results are unchanged, and there are no public API changes; the removed
transfer_lut_hacc_avx2was an installeddetaildeclaration. One commit per area:inlinecopy in an AVX2 translation unit.-1fallback convention. Everything stays inrescale_search.hppwith internal linkage.transfer_lut_hacc_generic, as NEON already does. The removed AVX2 version contained no vector instructions and wrote the same Pair32 layout; the outputs are byte-identical.RABITQ_RESOLVE_NEONreplaces 13 copies of the ARM64-NEON-or-RABITQ_RESOLVE#ifblock, whose ARM64 guards were inconsistent. Each target still references only its own ISA's symbols. The excode IP table keeps its explicit block, because it resolves whole tables.Tried and dropped, because each changed the code generated on a hot path for a small deduplication:
dim % 16check. It changed register allocation in the publicfastscan::accumulatewrappers.Testing
Linux x86-64 host: Xeon Gold 6418H, 2 sockets; GCC 14.3;
RABITQ_ENABLE_NATIVE_OPTIMIZATION=OFF.CTest (
--no-tests=error):RABITQ_USE_OPENMP=OFF: 173 passed.Static checks:
check-format.sh, fullcheck-tidy.sh build-tidy(clang-tidy 23) andgit diff --checkpass.Object code compared with
main(0734ec2), function by function:dispatch.cpp; all FastScan accumulate, pack and estimator functions;space_excode_avx2/avx512; and the AVX2 HNSW search kernels.Benchmarks (single thread, pinned to one idle core and its NUMA node, alternating with
main, 6–12 pairs):SplitBatchQuery::reset, d=128/960, standard and HACC: 0.95–1.01, same checksums.rabitq_core_benchmarkat 4 and 9 bits,encode_packedandprepare_query(which exercise the rescale search and quantizers): 0.94–1.02, same checksums.No speedup is claimed. Shared host: load average 4–11; CPU frequency was not locked.
NEON:
query_neon.cppand the macro's ARM64 branch indispatch.cpppass a clang--target=aarch64-linux-gnusyntax and semantic check, with no first-party errors. They were not built into object code or run.Not run locally: NEON execution, Windows and macOS builds.