Adding Versal interrupt support

pynqmetadata/models/proc_sys_core.py

@@ -1,4 +1,5 @@
 # Copyright (C) 2022 Xilinx, Inc
+# Copyright (C) 2022 - 2026 Advanced Micro Devices, Inc.
 # SPDX-License-Identifier: BSD-3-Clause
 
 from dataclasses import dataclass, field
@@ -137,6 +138,8 @@ def irq_map(self) -> List[int]:
         """Returns the IRQ map for this PS in the same way that the legacy Pynq metadata is expecting"""
         raw_map: List[int] = []
         for irq in self.irq:
+            if irq not in self.ports:
+                continue
             for base, num in self.irq[irq]:
                 for i in range(num):
                     raw_map.append(base + i)

pynqmetadata/models/versal_proc_sys_core.py

@@ -1,7 +1,7 @@
 # Copyright (C) 2026 Advanced Micro Devices, Inc.
 # SPDX-License-Identifier: BSD-3-Clause
 
-from dataclasses import dataclass
+from dataclasses import dataclass, field
 from typing import Dict
 
 from ..errors import ParameterNotFound
@@ -61,6 +61,16 @@ class VersalProcSysCore(ProcSysCore):
 
     type: str = "core-versal"
     ps_name: str = "versal_cips"
+    # PL to PS interrupts are one bit per port rather than a bus. Devices
+    # either expose one family, or split it by power domain with a different
+    # range for each. A design only carries the ports of its own family.
+    irq: Dict[str, object] = field(
+        default_factory=lambda: (
+            {f"pl_ps_irq{i}": ((116 + i, 1),) for i in range(16)}
+            | {f"pl_lpd_irq{i}": ((136 + i, 1),) for i in range(8)}
+            | {f"pl_fpd_irq{i}": ((175 + i, 1),) for i in range(8)}
+        )
+    )
 
     # Which parameter holds the packed configuration varies between boards and
     # cannot be told from the module type, so both are tried.

pynqmetadata/views/runtime/interrupt_controllers_view.py

@@ -1,4 +1,5 @@
 # Copyright (C) 2022 Xilinx, Inc
+# Copyright (C) 2022 - 2026 Advanced Micro Devices, Inc.
 # SPDX-License-Identifier: BSD-3-Clause
 
 import json
@@ -50,6 +51,9 @@ def _walk_for_irq_controllers(self, sig: Signal) -> List[Core]:
             idx = self._base_idx
 
         for dst in sig._connections.values():
+            # An interrupt can leave the design through a module boundary.
+            if not isinstance(dst.parent().parent(), Core):
+                continue
             if dst.parent().parent().vlnv.name == "axi_intc":
                 dst.parent().parent().ext[
                     "interrupt_controller_index"