Add initial support for CASPER (mlib_devel) designs

[jogomojo]

CASPER's user logic sits outside Vivado's IP Integrator, which is reachable through a single external AXI4-Lite manager port. PYNQ-Metadata was ignoring that entire address region since it targeted no known internal module.

This PR adds a generic fix so that when a manager port's range targets one of the design's own external ports, we create a placeholder IP block for it so the region shows up in ip_dict. This applies to any design with this pattern and requires no API changes.

This has only been tested against one mlib_devel design so far, verified on hardware (RFSoC4x2) with PYNQ (MMIO read/write of a few yellow-block registers). I don't plan to pull this PR in until it has been tested on more mlib_devel designs.

Limitations:

• No named register map. The .hwh doesn't include individual CASPER registers so users still need to add their own offsets.
• Reported addr_range is Vivado's default window is too small. Users need to size their own MMIO accordingly.