arch/arm/stm32f4: add STM32F412VG and STM32F412CG chip selections - #20006
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PX4/NuttX#399 now matches apache/nuttx#20006 on FSMC, timers, USART, I2S, and CE GPIOH. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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SPI4/5 and TIM6/7/10/11 are on the F412 die in every package (DS11139). FSMC is only bonded on 100/144-pin, so HAVE_FSMC is selected on VG/ZG and not on CE. Backport of apache/nuttx#20006. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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100-pin 1MB F412 (LQFP/UFBGA). Without this, boards using STM32F412VGH6 have to select the 48-pin 512KB CE. STM32_NGPIO is 113 rather than the real 81 I/Os because STM32_NGPIO_PORTS is (N+15)>>4 and 81 yields six ports A-F, so PH0/PH1 could not be configured. 113 matches ZG and gives A-H. CE/ZG chip.h counts and the family HAVE_* list are corrected in the same change: CE has no FSMC, the die has TIM6/7/9-14 and SPI4/5, ZG USART is 4, I2S is 5. FSMC is only bonded on 100/144-pin, so HAVE_FSMC is selected on VG/ZG and not on CE. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
48-pin 1MB F412. CE was the only 48-pin part listed, so boards using STM32F412CGU6 had to select a 512KB chip. Feature counts are identical to CE, so it shares the block. Assisted-by: Claude:claude-opus-5 Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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100-pin 1MB F412 (LQFP/UFBGA). Without this, boards using STM32F412VGH6 have to select the 48-pin 512KB CE. STM32_NGPIO is 113 rather than the real 81 I/Os because STM32_NGPIO_PORTS is (N+15)>>4 and 81 yields six ports A-F, so PH0/PH1 could not be configured. 113 matches ZG and gives A-H. CE/ZG chip.h counts and the family HAVE_* list are corrected in the same change: CE has no FSMC, the die has TIM6/7/9-14 and SPI4/5, ZG USART is 4, I2S is 5. FSMC is only bonded on 100/144-pin, so HAVE_FSMC is selected on VG/ZG and not on CE. Backport of apache/nuttx#20006. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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48-pin 1MB F412. CE was the only 48-pin part listed, so boards using STM32F412CGU6 had to select a 512KB chip. Feature counts are identical to CE, so it shares the block. Backport of apache/nuttx#20006. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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Summary
Adds
ARCH_CHIP_STM32F412VG(LQFP100/UFBGA100, 1 MB) andARCH_CHIP_STM32F412CG(UFQFPN48, 1 MB) to the STM32 chip choice, and corrects the adjacent F412 CE and ZG entries inchip.hfound while adding them.The choice previously listed only F412CE (UFQFPN48, 512 KB) and F412ZG (LQFP144, 1 MB), so parts such as STM32F412VGH6 and STM32F412CGU6 had to select CE. CE also advertised an FSMC the 48-pin package does not bond, omitted TIM6/7 and TIM9-14 that the die has, and used
STM32_NGPIO 34, which left GPIOH — the PH0/PH1 oscillator pins, usable as GPIO — outsideSTM32_NGPIO_PORTS. ZG claimed six USARTs while listing four. Per DS11139 Rev 9 Table 2 every F412 package has 2 advanced, 10 general-purpose and 2 basic timers, 5 SPI/I2S and 4 USARTs; the FSMC is bonded only on the 100- and 144-pin packages.VG takes
STM32_NGPIO 113rather than its real 81 I/Os becauseSTM32_NGPIO_PORTSis(N + 15) >> 4, and 81 yields six ports, A-F, dropping GPIOH. ZG already does this. CG shares the CE block, which is identical apart from flash size. The familyHAVE_*list gains SPI4/5 and TIM6/7/10/11, andHAVE_FSMCmoves onto the VG and ZG entries.Impact
g_gpiobase[]is now sized for eight ports and GPIOD-H are clocked. That is the point of the change: configuring a PH pin on CE previously indexed a three-entry array out of bounds. PX4's ARK CANnode has that pin disabled in board code with the reason written out ("Port H = 7 which is greater than STM32_NPORTS").Testing
Built out of tree in PX4, which carries this change as PX4/NuttX#399, with
arm-none-eabi-gcc 13.2.1on Linux:No on-hardware run yet.