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arch/tricore: mpu iLLD drop and per-set flags refactor - #20016

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arch/tricore: mpu iLLD drop and per-set flags refactor#20016
zhangyu-duck wants to merge 2 commits into
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zhangyu-duck:mpu

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@zhangyu-duck zhangyu-duck commented Aug 31, 2026

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Summary

Two commits on the TriCore MPU subsystem:

  1. mpu: per-set flags array and cpuset in mpu_region_s — refactor kflags/uflags into a per-set flags[] array indexed by set number, add a cpuset field to filter regions per CPU, and rewrite mpu_initialize to loop over all protection sets.

  2. drop mpu iLLD dependency and use raw register access — replace iLD union types and __mfcr/__mtcr intrinsics with uint32_t and tricore_mfcr/tricore_mtcr (from arch/tricore/include/arch.h); replace #ifndef CONFIG_ARCH_CHIP_TC3XX guards with per-case #if CONFIG_ARCH_MPU_NSETS > N / CONFIG_ARCH_MPU_DATA_NREGIONS > N / CONFIG_ARCH_MPU_CODE_NREGIONS > N guards; bump Kconfig defaults to HW full capacity (8 sets / 24 data regions / 16 code regions).

Impact

  • Architecture: arch/tricore (TC3xx / TC4xx)
  • Build: removes dependency on Infineon iLD headers for MPU register access; Kconfig defaults expanded to full HW capacity (8/24/16)
  • API: no public API changes; struct mpu_region_s layout changes (callers must update initializers — none in tree currently)
  • Behavior: no runtime behavior change; MPU initialization and region/permission programming logic preserved
  • Compatibility: no breaking changes for existing defconfigs

Testing

  • Build-verified on TC4xx defconfig (build_all.sh / make)
  • mpu_initialize logic reviewed: cpuset filter, per-set loop via mpu_modify_region(set, region, 0, 0, flags[set]) (relies on size==0 skipping base/size update), and else continue guard against stale region value when type bits are invalid
  • Bit-position correctness manually verified for mpu_control (CORECON.PROTEN = bit 1), mpu_get_active_set / mpu_set_active_set (PSW.PRS2 = bit 15, PSW.PRS = bits 12-13)

Signed-off-by: zhangyu117 zhangyu117@xiaomi.com

Refactor kflags/uflags into a per-set flags[] array indexed by set
number, and add a cpuset field to filter regions per CPU. Rewrite
mpu_initialize to loop over all protection sets.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@github-actions github-actions Bot added Arch: tricore Issues related to the TriCore architecture from Infineon Size: L The size of the change in this PR is large labels Aug 31, 2026
@zhangyu-duck zhangyu-duck changed the title arch/tricore: mpu iLLD drop and per-set flags refactor arch/tricore: mpu iLD drop and per-set flags refactor Aug 31, 2026
@zhangyu-duck zhangyu-duck reopened this Aug 31, 2026
@github-actions

github-actions Bot commented Aug 31, 2026

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MemBrowse Memory Report

No memory changes detected for:

Replace iLD union types and __mfcr/__mtcr intrinsics with uint32_t
and tricore_mfcr/tricore_mtcr. Replace the iLD-specific
to HW full capacity (8 sets / 24 data / 16 code regions).

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
@zhangyu-duck zhangyu-duck changed the title arch/tricore: mpu iLD drop and per-set flags refactor arch/tricore: mpu iLLD drop and per-set flags refactor Aug 31, 2026
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Arch: tricore Issues related to the TriCore architecture from Infineon Size: L The size of the change in this PR is large

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