arch/arm/ameba: add shared timer driver for RTL8721Dx/RTL8720F/RTL8721F - #20020
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xiaoxiang781216
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Add a parameterised NuttX timer lower-half for the Realtek Ameba general-purpose timers, sitting on the SDK fwlib RTIM register layer and registered at /dev/timerN. The shared driver (arch/arm/src/common/ameba/ameba_timer.c) reads a per-chip instance table (ameba_timer_chip.h) for each timer's base, input clock, RCC gate masks and IRQ; the period is programmed directly in microseconds and converted to the 32-bit auto-reload with one clkfreq formula. On the pke8721daf two of the 32.768 kHz "basic" (LTIM) timers are exposed: /dev/timer0 is TIM1 and /dev/timer1 is TIM2. TIM0 is left untouched because the boot ROM claims it as the always-on system timer (SYSTIMER); reprogramming it would break every SDK delay. The RTIM time-base entry points resolve to ROM, while the interrupt-clear and period-change helpers come from the fwlib RAM source ameba_tim.c (shared with the PWM driver). Verified on hardware with examples/timer against both devices: the update interrupt fires at the requested 1 s interval (measured with the independent ROM SYSTIMER = 32768 ticks = 1.000 s). Also whitelist the vendor RTIM_ symbol prefix in tools/nxstyle.c, alongside the existing RCC_/SYSTIMER_ Ameba SDK entries. Assisted-by: Claude <noreply@anthropic.com> Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba timer driver (arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0 (TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two 32-bit basic LTIM timers at 0x40808200 / 0x40808400, 32.768 kHz, APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h / sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up registration and a timer defconfig. The shared driver is unchanged. TIM0 is left untouched because the boot ROM claims it as the always-on system timer; reprogramming it would break every SDK delay. Assisted-by: Claude <noreply@anthropic.com> Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8721F (amebagreen2) into the shared Ameba timer driver (arch/arm/src/common/ameba/ameba_timer.c), registered at /dev/timer0 (TIM1) and /dev/timer1 (TIM2). Only the per-chip base addresses, RCC masks and IRQs differ, so this adds a small ameba_timer_chip.h (the two 32-bit basic LTIM timers at 0x40819200 / 0x40819400, 32.768 kHz, APBPeriph_LTIM1/2, IRQ_TIMER1/2, verified against the SoC hal_platform.h / sysreg_lsys.h / vector table) plus the Make.defs/CMakeLists build hooks, the fwlib ram_common/ameba_tim.c RAM source (now also pulled in by CONFIG_AMEBA_TIMER, matching the PWM rule), the board bring-up registration and a timer defconfig. The shared driver is unchanged. TIM0 is left untouched because the boot ROM claims it as the always-on system timer; reprogramming it would break every SDK delay. Assisted-by: Claude <noreply@anthropic.com> Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
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Summary
This PR adds a shared NuttX timer lower-half for the Realtek Ameba
general-purpose timers and wires it into three boards (RTL8721Dx, RTL8720F,
RTL8721F).
The shared driver (
arch/arm/src/common/ameba/ameba_timer.c) sits on the SDKper-chip instance table (
ameba_timer_chip.h) for each timer's base address,input clock, RCC gate mask and IRQ; the requested period is programmed
directly in microseconds and converted to the 32-bit auto-reload with a single
clkfreq formula. The RTIM time-base entry points resolve to ROM, while the
interrupt-clear and period-change helpers come from the fwlib RAM source
ameba_tim.c(shared with the existing PWM driver, now also pulled in byCONFIG_AMEBA_TIMER, matching the PWM build rule).On each board two of the 32.768 kHz "basic" (LTIM) timers are exposed:
/dev/timer0is TIM1 and/dev/timer1is TIM2. TIM0 is deliberately leftuntouched because the boot ROM claims it as the always-on system timer
(SYSTIMER); reprogramming it would break every SDK delay. Only the per-chip
base addresses, RCC masks and IRQs differ between the three SoCs, so each chip
adds only a small
ameba_timer_chip.h(verified against the SoChal_platform.h/sysreg_lsys.h/ vector table) plus its build hooks, boardbring-up registration, board
timerdefconfig andindex.rstdocs. Theshared driver itself is identical across all three.
The
timerdefconfigs also enableCONFIG_TIMER_ARCH=y; without itup_timer_set_lowerhalf()expands to a no-op macro,systick_initialize()isnever called and
clock_systime_ticks()never advances.tools/nxstyle.cgains the vendorRTIM_symbol prefix in the whitelist,alongside the existing
RCC_/SYSTIMER_Ameba SDK entries.Impact
New optional peripheral driver, off by default (
CONFIG_AMEBA_TIMER). Nochange to any existing board configuration. Only affects the three Ameba
boards listed above.
Testing
nxstyle/checkpatchclean on all three commits.makeandcmakeout-of-tree builds pass for all three boards with the:timerconfig.examples/timeragainst both
/dev/timer0and/dev/timer1: the update interrupt fires atthe requested 1 s interval (cross-checked against the independent ROM
SYSTIMER = 32768 ticks = 1.000 s), and
cat /proc/uptimeadvances in realtime (the example completes in ~2 s with nsignals=2, confirming the system
tick is running).