drm/apple: 4K at 120 Hz on the M4 MacBook Air external displays

Documentation/devicetree/bindings/display/apple,dcp.yaml

@@ -119,7 +119,10 @@ properties:
           - description: Index into the provider's reg property.
           - description: Index in the firmware display register table.
           - description: Byte offset of the scratch register within the resource.
-    description: PMGR bandwidth scratch resource, display index and offset.
+    description: |
+      PMGR bandwidth scratch resource, display index and offset. On the T8132
+      external DCPs it is the pipe's 8-byte realtime bandwidth request slot,
+      which lies inside the display register window the index names (disp-4).
 
   apple,bw-doorbell:
     $ref: /schemas/types.yaml#/definitions/phandle-array

arch/arm64/boot/dts/apple/t8132-j713-dcpext.dtsi

@@ -5,7 +5,8 @@
  * T8132 has two external display pipes, dispext0 and dispext1, each with
  * its own DCP, mailbox, DCP DART and display DART. They mirror the
  * internal display (t8132-j713-display.dtsi) at other bases and share its
- * firmware clock window (disp-4).
+ * firmware clock window (disp-4), which also holds their realtime bandwidth
+ * request slots in the PMC.
  *
  * iBoot starts both and leaves them quiesced, as it does the internal one.
  * When the boot loader hands them over (opt-in, and only after the internal
@@ -81,6 +82,7 @@
 		power-domains = <&ps_dispext0_cpu>;
 		dma-noncoherent;
 		apple,dcp-index = <1>;
+		apple,bw-scratch = <&pmgr_dcpext 0 4 0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 
@@ -91,6 +93,17 @@
 		};
 	};
 
+	/*
+	 * The external pipes' realtime bandwidth request slots in the PMC,
+	 * 0x2c000 and 0x30000 into the window the dcpexts have as disp-4.
+	 */
+	pmgr_dcpext: power-management@38282c000 {
+		reg = <0x3 0x8282c000 0x0 0x8>,
+		      <0x3 0x82830000 0x0 0x8>;
+		reg-names = "dcpext0-bw-scratch", "dcpext1-bw-scratch";
+		#apple,bw-scratch-cells = <3>;
+	};
+
 	dcpext1_mbox: mailbox@48ae08000 {
 		compatible = "apple,t8132-asc-mailbox", "apple,asc-mailbox-v4";
 		reg = <0x4 0x8ae08000 0x0 0x4000>;
@@ -142,6 +155,7 @@
 		power-domains = <&ps_dispext1_cpu>;
 		dma-noncoherent;
 		apple,dcp-index = <2>;
+		apple,bw-scratch = <&pmgr_dcpext 1 4 0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 

drivers/gpu/drm/apple/dcp-m4-callback.h

@@ -21,6 +21,11 @@ struct dcp_m4_callback_ops {
 	int (*memory)(void *cookie, unsigned int method, const void *input, void *output);
 	/* Idle caching: D117 state, D578/D579 fence, D580 cache-surface release. */
 	int (*idle)(void *cookie, unsigned int method, const void *input, void *output);
+	/*
+	 * D003 rt_bandwidth_setup_ap: its reply, @output zeroed (0x3c bytes).
+	 * Absent: the optional service is declined (status 1).
+	 */
+	int (*bandwidth)(void *cookie, void *output);
 };
 
 struct dcp_m4_callback_shape {
@@ -129,6 +134,8 @@ static inline int dcp_m4_callback_dispatch(const struct dcp_m4_callback_ops *ops
 		put_unaligned_le32(1, out);
 		return 0;
 	case 3:
+		if (ops->bandwidth)
+			return dcp_m4_callback_result(ops->bandwidth(cookie, out));
 		put_unaligned_le32(1, out + 56); /* Decline optional bandwidth service. */
 		return 0;
 	case 6:

drivers/gpu/drm/apple/dcp-m4-frame.h

@@ -404,4 +404,21 @@ static inline int dcp_m4_swap_take_completion(struct dcp_m4_swap_state *swap)
 	return 1;
 }
 
+/*
+ * Hand a replied swap over to @to, which tracks it from then on (its D590 may
+ * be in already): @swap counts as taken, so that the next swap may begin.
+ */
+static inline int dcp_m4_swap_hand_off(struct dcp_m4_swap_state *swap,
+				       struct dcp_m4_swap_state *to)
+{
+	if (swap->error)
+		return swap->error;
+	if (!swap->id || !swap->replied || swap->emitted)
+		return dcp_m4_swap_fail(swap, -EPROTO);
+	*to = *swap;
+	swap->completed = true;
+	swap->emitted = true;
+	return 0;
+}
+
 #endif