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arm64: dts: apple: describe disabled T8112 resources on merged bindings - #1148
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Keep the existing T6041 and T8140 resource layouts while adding the M2 variants. Reuse the generic platform bindings and describe the existing M2 firmware transports without adding diagnostic service devices. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Add the missing media, DMA, fabric, cache, SPMI and board resources, and correct the AVE physical address translation. All new controllers remain disabled. Leave the J413 board description to its existing owner. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
The firmware audio interface retains its existing PMGR reset-domain phandle. Declare its phandle-array type so schema assembly can decode the property. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
Later-generation AOP nodes advertise a T6020 transport fallback but use different service compatible lists. Select this binding only for the single-compatible M2 nodes so it does not impose M2 service contracts on those later generations. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
RyanTheTide
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November 7, 2026 15:43
Retain the merged DCP and NVMEM cases, extend disabled resource forms, and reuse canonical T8112 SPI/SPMI controllers. Keep J413 auxiliary PMIC ownership in its board file; describe the other Vale instances in their board resource includes. Remove duplicate auto-merged T8112 enum entries. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
RyanTheTide
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November 7, 2026 15:58
RyanTheTide
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November 7, 2026 16:39
Union and sort shared compatible entries, preserve merged M3 and legacy contracts, and constrain AES, scaler, AVE and ProRes layouts per generation. Keep reference-Mac descriptions unchanged. Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
RyanTheTide
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November 7, 2026 17:01
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November 7, 2026 17:29
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…cription Merge train 11-08: DT2 ready (dt-check 0 new, describe-only). On the merged tree the t6040-j616s and j614s DTBs are unchanged (no diff besides phandles), the t6041 j616c and j614c DTBs gain 10 disabled nodes each with none effectively enabled, and W=1 equals base (13/13, 5/5). CI dt-checks + host-tests green; clean on the tip after #1148.
This was referenced Nov 7, 2026
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Take #1132 (disabled M4 Max scalers), #1148 and #1105 (panel gamut from the ADT), and carry their M4 changes into the new layout: - ps_msr0's ps_msr0_dart label and comment, and scaler0_dart's power-domains = <&ps_msr0_dart>, go to t6040-pmgr.dtsi and t6040.dtsi, where those T6040-only nodes now live; - t6041-j614-j616-j575-scaler.dtsi is included by the J614c and J616c board files, after t6041.dtsi as before; - apple,color-gamut goes from the shared J614c/J616c panel. Each M4 dtb differs from the integration/aurora tip exactly as it differed from this branch's previous base. Signed-off-by: Diljit Singh <hey@djdev.me>
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Brings aurora-wip up to the 11-08 morning integration tip: DT descriptions for every Mac family (#1094, #1097, #1111, #1131, #1132, #1148, #1149, #1155, #1156, #1157, #1172), the J616s scaler (#1168), the panel primaries from boot data (#1105), AVD macOS command parity (#1116), AVD dma-coherent (#1169), the M2 PMU RTC alarm (#1151), G17 admission without spinning (#1146) and the AOP map wait (#1147). Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Assisted-by: LLM
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T8112 trees omit media, DMA, fabric and cache resources, and disabled AVE/DART windows use bus offsets as physical addresses. Add disabled descriptions and correct those addresses. Reuse canonical SPI/SPMI controllers, retain J413 auxiliary PMIC ownership in its board file, and describe other confirmed Vale instances in board-local includes.
Current head 3961756.
Verified by controller buildbox h-50458, completed rc=0, using the original full-catalog apple-dt-check.sh (SHA-256 9f586331dfd7) as explicit merges into integration 95e30d5:
Compatible enums are the sorted M2/M3 union. AES/scaler/AVE/ProRes constraints retain generation-specific layouts and the existing legacy cases. Integration 95e30d5 is merged with ordinary merge commits, no force push. #1094 reference-Mac descriptions and canonical labels are retained; J413/J316s board files are unchanged from that integration source. New controllers remain disabled; firmware/debug endpoints are waived. No target boot/peripheral qualification is claimed. Audit/private inputs stay outside the kernel repository. Baseline catalog diagnostics remain; the comparison introduces none.
Replaces #1118. M2 Pro/Max/Ultra resource work is in #1149.
Supplementary audit of the exact verified DTBs passes rc=0: 290/290 register/IRQ/applicable IOMMU facts, canonical controllers and disabled Vale PMICs, complete Ultra host register/PCIe-memory translations, and zero selected vendor-contract diagnostics across 194 collected SoC DTBs. The required full-catalog check above is unchanged.