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arm64: dts: apple: t6050: describe the rest of the M5 Pro/Max/Ultra hardware, add J714s, J775c and J873s - #1202
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Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Describe translated MMIO, IRQ, DMA, clock and PMGR resources for the T6050 board inventories. Keep unqualified devices and providers disabled. Preserve the existing J775d boot profile and third-party base history; add no firmware, calibration or programming data. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Decode the live hardware-reference representation, retain the separate display engine identity and collect native EDAC status apertures. Keep each new schema variant closed while exposing its property types at the root. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Restrict inherited selectors to their compatible properties, retain the existing ANE conditional semantics with an explicit empty then branch, and use the Samsung/Apple UART binding. Correct SPMI child addressing and the disabled AIC3 and timer descriptions. Omit zero-length ANS template slots. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
…isites Carry forward the licensed public T6050 binding work from d87e84f while retaining the merged family contracts. Describe the existing J775d handoff interfaces, including combo PHY, N1 control, AOP audio and PMGR consumers. New inventory variants remain disabled; this changes no DTS enable policy or driver source. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Accept the existing J775d fallback sequences without changing the independent disabled resource forms. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Describe the shared PWM register bank once with both interrupt and gate relationships. Keep distinct audio DMA proxy views, expose legacy pattern-property types at binding roots, and normalize generated YAML. Resolve the public profile contracts without adding enables or changing driver code. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Keep the four-stream native transport in its closed alternative and retain the original DMA-name limit only in the original interface. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Use the published T6050 CPU-class affinity mapping with the ADT cluster/core affinities, retaining all CPU inventory disabled. Include the optional J775d die-1 CPU records. Resolve the notebook FPWM1 NoPS vote through its native parent and omit the invented independent state on those templates. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Drop an obsolete four-port pattern carried by the older T6050 prerequisite snapshot. The merged T6040 PCIe-C contract keeps its six interrupt names; the T6050 disabled alternatives and boot profile are unchanged. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Both EC proxy ADT identities publish the same complete hardware register view and no distinct IRQ, clock or DMA route. Retain one disabled physical bank; downstream service separation remains in the gap ledger. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Integration now has the reviewed T6050 trees: the SoC and J775D, the J716c and J714c, the J716s and the K114/K116. Rebuild the inventory on top of them: - Every board, old and new, includes t6050-peripherals.dtsi after its own description, with its T6050_<BOARD> define. The J714s, J775c and J873s are new board files on t6050-max.dtsi with PCIe port 0 off; their model strings are the ADTs' product names. The scaffold SoC file this branch used for them (t6050.dtsi, t6050-pmgr.dtsi) goes, the one-die media PMGR and video decoder DART it provided move into the inventory, disabled. - Inventory nodes that a board's tree already describes are dropped for that board: same path, same label or the same first register window (the SPMI buses, display crossbar, MTP and its DART, FPWM, the ATC3 USB4 router, NHI and DART, the ATC PHY coprocessors). Several of them sat at the same path as a reviewed node and would have overridden its properties, the FPWM power states among them. The compiled tree of every board that existed before is unchanged, node for node and property for property; the inventory only adds disabled nodes. - The shared bindings keep their integration form. This branch had rewritten 53 of them; the T6050 entries the inventory needs are added to them separately. The six bindings it added for blocks nothing described before stay, without the status constraint. - The inventory's SPMI buses use the T8142 fallback, as the reviewed SPMI nodes do. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Picks up the J716s ADT coverage inventory, so the ratchet measures what the inventory adds on that board. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
… nodes are Several inventory nodes described a block in a shape of their own where the reviewed T6050 trees, or the same block on other SoCs, already have a Linux form. Rework them from the same ADT records: - The external display coprocessors (dcpext1-3) and the internal DCP take dcpext0's form: the ASC, the display engine's five windows and iop-vbar in one node, the ASC v4 mailbox at +0x8000 with the first four ADT interrupts in mailbox order, the DCP and display DARTs. The separate display-engine nodes go, their windows are in the DCP now. - ADMACs use the T8140 fallback with dma-channels from the ADT channel counts and the AP's interrupt in the first of the four outputs, as admac_base_ns does. - DARTs with several instances (ISP, ANE, AVE, the ATC0 USB DART) are split into one node per instance, as on T8140, each with the auxiliary window that belongs to it; their consumers use stream 0 of each. - The ATC0 USB controller takes usb_drd2's register split. The ANE takes the T6041 register names and layout, which it shares. The PMP is "apple,t6050-pmp-v2", the family the PMP driver matches. The GPU block is "apple,agx-t6050". The AUSS USB controller is not a dwc3 and gets its own compatible. The display crossbars and the DisplayPort PHY take the reviewed T6050 compatibles and cells, the AON PTD the interrupt controller cells of T8142/T8152, the UART its clock names. - Dropped: the MTP DockChannel (t6050-max.dtsi has it), and the ATC0-2 USB4 routers, ATC PCIe-C hosts and the raw ATC0 PHY record. Describing those properly needs data the static ADTs do not carry (the routers' firmware SRAM window) or a combo PHY description per port; they are left for that work instead of being described in a second shape. Everything stays disabled. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Describe the T6050 blocks of t6050-peripherals.dtsi in the shared Apple bindings, with the register and interrupt counts of the ADT records: - Added to existing entries with the same shape: AES (T6041's three windows), AIC timebase, AON PTD, DisplayPort input, PCIe and PCIe-C PIODMA, SPI, PMGR clocks (60 windows), RSM (T6032's), secure mailbox (T8142's), UART (T8140's), DCP and DCP expert, AVE, JPEG (T8132's), ProRes (two or five windows), AOP2, the secure ADMAC. - With a T6050 branch: the SoC error handler (214 windows, 105 interrupts) and event log (141, 23), the SIO (two windows, four interrupts), the SEP (its mailbox interrupts, no mailbox node yet), the PMP v2 (four windows and interrupts, two power domains), the ANE (the T6041 layout, three clocks, one power domain) and the GPU block. - New: the T6050 ISP, whose ADT node lists the coprocessor and two PMGR windows instead of in-block mailbox windows, and the AUSS USB controller. Properties only a driver needs (resets and role switching for dwc3, the SEP and PMP mailboxes, the GPU's firmware regions, the secure ADMAC's channels and interrupt) are required for enabled nodes only, as the ISP binding already does, so a disabled description from the ADT validates. The display engine binding goes, as nothing uses it now. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
Regenerate the J716s ADT coverage inventory against the J716s tree with the T6050 inventory included. MISSING drops from 941 to 700, mapped rises from 155 to 516; the inventory still lists the same 1603 devices and every DT path in it exists. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com>
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The rest of the T6050 (M5 Pro, M5 Max, M5 Ultra) family on top of the trees now in integration: #935 (T6050 and the J775D), #945 (J716c and J714c), #1167 (J716s) and #1025 (K114/K116).
What it adds
t6050-peripherals.dtsi, the hardware each board's ADT lists that the SoC and board files don't describe yet, as disabled nodes: the internal DCP and external DCPs 1 to 3 with their mailboxes and DARTs, ADMACs, SIO, SPI, UART, PIODMA, ISP, ANE, the GPU block and its coprocessor, ProRes, JPEG, AVE, the scaler, SEP, PMP, the error and event log handlers, the ATC0 USB controller and more. Every board includes it with its ownT6050_<BOARD>define, so a board only gets the blocks its ADT has.t6050-max.dtsi: the J714s (MacBook Pro 14-inch, M5 Pro), J775c (Mac Studio, M5 Max) and J873s (Mac mini, M5 Pro). Beyond the SoC they carry only the disabled inventory; PCIe port 0 is off. Nobody has booted them.How it was put together
DT3 staged the inventory on #935 alone. Merged with the reviewed trees, some of it described hardware a second time and some sat on the path of a reviewed node, so those are dropped per board. Where the inventory had its own shape for a block that already has a Linux form (the DCPs, ADMACs, multi-instance DARTs, the ATC0 USB controller, the ANE, the PMP), it now uses that form, built from the same ADT records. Bindings are extended, not rewritten: properties only a driver needs are required for enabled nodes, as the ISP binding already does.
Left out on purpose
Where the values come from
Register windows, interrupts, DMA streams, channel counts and power-state offsets come from the boards' ADTs. No firmware, tuning or calibration data is in here.
Checks
make W=1for all eleven T6050 boards: no dtc warnings.CHECK_DTBS=yon every Apple DTB: no new warnings, and none on the T6050 boards.dt_binding_checkon every binding this touches.Build-tested, unbooted. We have no T6050 here.
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