[joshuaswarren]

Gives the 14-inch M5 Max (J714c) its left-front USB-C port. It builds on #1391 (the right port) and is one commit.

What changes

t6050-j714c.dts stops disabling the ATC1 template of t6050-dieX.dtsi (atc1_phy_mbox, atc1_phy, usb_drd1, usb_drd1_dart_0/1) and nub_spmi_a0. It adds the PD controller usb-pd@a (SN201202x, SPMI address 0xa) with its usb-c-connector, the endpoint links to atc1_phy and usb_drd1, and the atcphy1 alias. nub_spmi_a2 and the ATC3 nodes stay disabled.

Why only ATC1

The J714cAP firmware ADT (27.0) has two PD controllers on nub-spmi-a0:

ADT node	SPMI address	port-number	port-location	acio-parent	ATC
hpm0	0xc	1	left-back	acio0	ATC0
hpm1	0xa	2	left-front	acio1	ATC1

The ATC1 PHY, DWC3, DARTs and mailbox already exist as the die template. I checked the PHY core, usb2phy and usb2-digital addresses against the J714cAP ADT's atc-phy1 registers; they match.

ATC0 (hpm0, left-back) is not described, on purpose. The combo PHY binding limits apple,port-index to 1-5 ("the debug port (0) is excluded"), and atc-t6050-dp.c returns -EINVAL for port 0 ("the debug port that carries the boot link"). A PHY node for ATC0 fails dt-validate and would fail to probe. Decision: Linux does not take that port, so the USB-C VDM reboot and recovery path through the left-back port stays usable. Describing it later needs a binding and driver change first.

Testing

Offline only:

• All 11 T6050 board DTBs build with dtc, no errors or warnings.
• Against the base tree (066933561b1c), the ten DTBs other than the J714c are byte-identical (cmp). The J714c is the only change.
• dt-validate of the J714c DTB: base 1 warning, now 1, the same one (pcie@1c70000000: False schema does not allow ['port0']; the J716c DTB has it too). I built the schema without phy/ti,cd2e22.yaml, which clashes with the Apple apple,tunable bindings at base.

Not tested

• No J714c hardware boot. The port is not run on a J714c.
• The PHY and DWC3 tunables are the template's, which the boot loader overwrites through atcphy1; they were not compared with the J714cAP ADT values.
• The port's USB4/Thunderbolt router (acio1, dart-acio1, acio-cpu1, NHI, PCIe tunnel) and its DisplayPort routes are not described. The PHY runs in USB mode.
• The ADT's usb-drd1 lists a fifth interrupt (846) and usb-restore-disable. The template ignores both.
• hpm5 (ADT port-type 17, not a USB-C port) is not described.
• No left-back, audio or ANE change.

[chatgpt-codex-connector]

Codex Review Summary: ❌ Failed

This comment shows the latest Codex review activity on this pull request.

Review	Status	Commit	Review trigger
📝 Code Review	❌ Failed 2026-11-10T02:09:49.444034Z We couldn’t complete this review. Comment @codex review to try again.	5014b38	PR opened
🔒 Security Review	❌ Failed 2026-11-10T02:09:56.320670Z We couldn’t complete this review. Comment @codex security review to try again.	5014b38	PR opened

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[joshuaswarren]

GREEN at 5014b38

opencode-go/glm-5.3-flash as routed by Main (model id unverifiable); implementer model unverified.

Reproduced the CI check script locally (CHECK_DTBS on all 137 Apple DTBs, base 0669335 vs this head): 0 new warnings. Of the 11 t6050 DTBs only t6050-j714c.dtb changes; the other 10 are byte-identical to base. The new hpm1 node mirrors the accepted hpm2 pattern (apple,sn201202x, SPMI_USID address, usb-c-connector with the high-speed and super-speed ports, no DP route, consistent with the stated PHY-in-USB-mode scope). The ATC1 template nodes carry no disabled status, so deleting the board's disable overrides enables them; the combo PHY's probe contract (apple,port-index <1> on die 0, apple,guest-port-reserved, mode-switch) is satisfied by the template, and the debug-port exclusion for index 0 in the driver matches the PR's scope note. Not verified: runtime bring-up on hardware.