[satchlj]

GPT-6.1 Sol on @satchlj's behalf

Mask PCIE_LINK_STATE_CLKPM before enabling endpoints on the adopted T6050 host, then walk the enumerated bus to retain that policy. Firmware owns CLKREQ# pads and reference-clock gating here; suppressing L0s/L1 capability bits alone does not mask Clock PM. This is the isolated sufficient boot fix, without the private bus-number, NVMe or suspend/PME changes.

Scope: only t6050_hw (apple,t6050-pcie) sets adopt_link. This covers native M5 Pro/Max/Ultra adopted hosts, including J714/J716 and J775 boards; the separate PCIe-C/tunnel match data and earlier SoCs do not select it. J714/J716 results are not known to us.

Hardware evidence from Satya's J775c Mac Studio M5 Max bisection (2026-11-11/12): plain integration 716670b987b23536eafea3b647ffa7f28ef762b7 did not return from boot with the retained candidate44 DT or the attempted ported layout. Bus-number preservation alone automatically returned to the default, not as the trial, and was insufficient; old NVMe alone also failed. Clock PM suppression alone at b88dec9637cf3e4ce56d7b146af907ef4d58ff5f, kernel build #6, returned as the trial with management Ethernet, Wi-Fi and root NVMe, using installed Aura b6e6faf4.

That kernel also passed the final incremental DT 9c038a05a1aaf2c2722ca1e354b24125011c0f7c, source DTB SHA256 bffee06f90270ddb50d933082bdff86f01447a979e470521d5209ea492b0bb84: CPUs0-17, 62GiB, root NVMe, wired/Wi-Fi, USB2/3 hubs and microphone, HDMI connected, USB audio plus two display audio cards, GL9755, four router DT statuses okay, TB20Gbps to alba in both directions and renderD128. SDDM/NetworkManager/sshd active, zero failed units after a userspace stable-sysfs-path service fix. This is enumeration/health evidence, not playback or device stress qualification.

Rebased onto freshly fetched integration de6a8d46f755237a012435a735251a5efb325d34. This exact rebased kernel has not been booted. Original author Satya Benson is retained, deriving from his candidate44 caf39be510c0c54ddce8b077021f05b890608683 Clock PM policy; DCO signoff and Assisted-by retained.

Offline: Clang18 arm64/16KiB drivers/pci/controller/pcie-apple.o builds on this exact head (AArch64 ELF verified); checkpatch0 errors/1 commit-prose warning; whitespace check passes. No DT or binding paths edited, so DT/binding checks are not applicable to this driver-only PR. Host details: repository full runner on this exact head completed 248/255 initially; all seven failures were absent historical-object/path controls. After fetching their Aurora fixture revisions, all affected controls passed on this exact head (bcm4377-id1/1, compute-preempt2/2, dma-heap-fd1/1, g15-input-error3/3, neo-auxiliary3/3, neo-stability10/10). This is a complete initial run plus targeted successful reruns, not a second monolithic255/255 run. VM tools are Python3.12.3/Rust1.93.1/Clang18.1.3, differing from hosted CI Python/Rust pins; no hosted-CI equivalence claim.

Not covered by this bisection: HDMI replug, audio playback (analog AOP card absent with integration), SD media/physical hotplug/discard, RTC wake or suspend qualification. Historical candidate44 tests are not attributed to this head. The Thunderbolt recovery driver series is separate: R3 booted but stop/start soak failed cycle3 after two passes, not25/25; freezer0/5. No other-board regression result is claimed.

🤖 Generated with Codex (GPT-6.1 Sol)

[RyanTheTide]

@satchlj This conflicts with integration/aurora now, please rebase. Two notes on the code: apple_pcie_adopted_no_clkpm() does not need pcie->lock, so please call it before mutex_lock() in apple_pcie_enable_device(). And since this turns Clock PM off on every adopted T6050 link, we need a boot and s2idle result from a J714s and a J716c as well as your J775c on the rebased head before it can go in.

[satchlj]

GPT-6.1 Sol on @satchlj's behalf

Merged fresh integration/aurora 6970a51ef8c3fac411fab8b9b242b85b8324b8ab into this branch with merge commit e52e386dc26174cafe3d14f3e8722671c1eba0c4 (parents bb464b0c13c22c1dcf82ad9edd92897639ac26b9 and integration above); fast-forward push only, with the fork branch fetched again before pushing.

Resolved the single PCIe overlap by retaining the complete upstream Neo helper block and then the complete Clock PM host-init wrapper, preserving both the pre-enable mask and post-enumeration walk; no relocation or semantic change was needed.

Native lobata checks: net diff against integration touches only pcie-apple.c; checkpatch 0 errors/0 warnings, whitespace clean, exact PR-head PCIe object builds as AArch64. Full native kernel build passed with existing warnings.

One-shot boot passed on J775c with #1619 0075a007a50701db8cb2ac8aab5f6910377ed414; combined boot commit 4da06bc2a1bdeb0eaac1119fbddd1f7f55d97f11, Image.gz SHA256 41ce78c0b1eb1444e3c4d9e32ed9f1e7db0e8b9b64bf9ff728e37e664e5a9348, ANE-wrapper DTB SHA256 0a4ec6fdb639e9eedb4e0736419ba2a847879b3fe2c1a10af54cdfaa74befa28, config SHA256 58c6362ff6b3183b8a93ba39882f953074cd75547efe9fb234be6929761d5162. Actual trial kernel 7.3.0-lobata-refresh1618+ #1, boot ID 94a317b6-b638-4bb5-9dd2-217eaf37c5ec, arm64.nomte retained. SSH returned; /dev/nvme0n1p7 root ext4 rw; PCIe Centauri Wi-Fi 0000:01:00.0 (106b:1900) and RTL8127 Ethernet 0000:03:00.0 (10ec:8127) bound with IPv4; wired gateway ping 3/3. Kernel logs show Clock PM off: the host does not handle CLKREQ# for 01:00.0, 02:00.0 and 03:00.0; no PCIe AER errors or SError in complete collected boot logs; zero failed units.

Default candidate44 #25 restored healthy, trial marker spent, all seven protected hashes unchanged (installed Stage2/default/fallback/support payloads), Stage1 untouched, build directories removed and lock released. No failing control repeated, suspend, poweroff or recovery power cycle. This is boot/enumeration health evidence on J775c, not suspend or other-board qualification. Fresh hosted host-tests queued at publication; no review requested.