[aeries0x]

External displays on the J604 (MacBook Pro 14", M4) over USB-C in DisplayPort alt mode, as asked about in #1518.
Today the T8132 PHY refuses DP outside USB4/TBT, so a USB-C monitor or a USB-C to HDMI hub gets no picture.

Four commits:

1. phy: apple: atc: DisplayPort alt mode on T8132 — on a port marked apple,dp-alt-mode, 4-lane DP and
   USB3+DP run the PHY's own DP transmitter: the DP lanes and AUX sit in the core window at the offsets the T8122
   helpers use, and the T8122 AUX and main-link sequences bring them up. set_mode(DP) accepts any submode (the
   crossbar picks the DCP), the DCP's link rate goes to the T8122 link start, drive requests leave the lanes at their
   start level (no dp-training-table on these PHYs). Ports without the property behave as before. The binding
   gets the property; the host-test fixtures that compile the touched functions get the new field and helper, and
   atc-usb3-tests a T8132 target-mode case.
2. drm: apple: fabric — a T8132 dcpext route counts as "no DP alt mode" only when its PHY lacks the property;
   a routed dcpext connects on HPD from the Type-C reconnect work, and its direct crossbar output gets its link up
   as on T6030. A dcpext stays no appledrm pipeline either way: appledrm keeps skipping its ports and they take no
   tiles. Fixture updates for tiled-split-tests and the apple-dcp transaction harness.
3. arm64: dts: t8132-j604 — both dcpext pipes with routes to all three USB-C ports (left ports as on the
   J713, right port on ATC3 with its crossbar) and the three PHYs marked. HDMI (ATC2) is not part of this.
4. phy: apple: atc: T8132 DP lane start — the T8132 lane start differs from the T8122 one in three points
   (start drive preset on both blocks, RX VREF filter held over both DTVREG stages, no LDOCLK1 bypass at HBR3);
   passed as flags to the shared lane start, T8122 callers unchanged. It is separate so it can be dropped on its own:
   in my tests both starts trained (below).

The enable comes from the board DT only; no module parameter. As on the J713, a pipe is only used when aura hands
it over (chosen.asahi,j713-dcpext=1), and the internal display still needs the DCP opt-in.

Tested on the J604 with these four commits on integration/aurora 2b4523c plus #1483, #1543 and two local
test-only commits (RTC read-only, a GPU counter):

• All three USB-C ports (right, rear-left, front-left), Dell S2722QC over USB-C: 3840x2160@60.
• Right port, UGREEN CM512 hub (pin D) to a Dell's HDMI input: 1920x1080@60, both plug orientations.
• The internal display stays on appledrm throughout.

Earlier, the first version of this PR (the same commits except the two appledrm/tile checks in commit 2) on
integration/aurora 716670b, with a local runtime switch to compare the lane start of commit 4 against the plain
T8122 one:

• Right port, Dell S2722QC over USB-C: 4 lanes at HBR2, 3840x2160@60, both plug orientations, with both lane starts.
• Right port, the same hub: HBR3, 1920x1080@60, with USB 3 at 5 Gb/s on the same port (hub, Ethernet adapter, card
  reader, stick), with both lane starts.
• Rear-left port, Dell over USB-C: 4 lanes at HBR2, 3840x2160@60.

Not tested: suspend/resume with a monitor attached, two monitors at once.

Assisted-by: LLM

[aeries0x]

Force-pushed: rebased onto integration/aurora 2b4523c, with a fix in commit 2. The first version changed dcp_typec_route_no_dp_alt(), which dcp_typec_port_unusable() and dcp_typec_port_untileable() also use in the sense "a T8132 dcpext". With a DP alt mode PHY on a port, appledrm then looked for a pipeline of its own for that port, found none and did not bind ("Type-C port 0 has no display pipeline", -ENODEV), so the internal display stayed on simpledrm. On the old base appledrm happened to bind before the dcpext routes were registered, so I did not see it; on the new base it no longer does. Both checks now use dcp_is_t8132_ext(). Retested on 2b4523c; the description has the details.

On the boot-logo stop mentioned in the first version: #1616 and #1617 enabled the T8132 scaler and JPEG DARTs without power-domains. A bisect on the J604 landed on those two merges, and #1668 (654fad4) already fixed it, so the new base boots.

[RyanTheTide]

The T8122 helpers keep their old sequence for every non-T8132 caller (flags 0), and the fabric changes are all T8132-dcpext gated. The J604 results across the three ports cover it. Looks good.