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media: apple: avd: dispatch queued work across codec VP pools - #711
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RyanTheTide wants to merge 10 commits into
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RyanTheTide wants to merge 10 commits into
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Cap admitted slots at the match-data FIFO budget and submit packetized programs through open firmware ABI 2. Give each slot independent FIFO storage and let firmware select an available engine from its codec pool. Keep predecessor-complete dependencies as the default, serialize PP work, and reset before retiring fatal firmware errors. Release the m2m job when a complete picture owns its buffers so separate contexts can run concurrently. Preserve codec-specific PP work counts, which can differ from VP program segments. Add FIFO-limit and PP-count KUnit cases plus a host test linking the real firmware scheduler. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Add the document license tag and format the native integration test. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Require the device DMA domain before enabling queued PIODMA work and stop the CM3 when ABI or pool validation fails. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the accepted power-idle recovery and FIFO admission changes. Share the PM-owned PIODMA mapping and replay, release queued DMA storage before final DART shutdown, and retain the T6040 codec capability requirement while selecting its v5-t2 image. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
RyanTheTide
changed the base branch from
avd/rewrite-core
to
avd/rewrite-integ
October 31, 2026 13:33
Recognize ABI 1 images without submitting ABI 2 records to them. Keep the existing one-frame transport when DT cannot supply queued PIODMA mappings, so source and DART requirements remain enforced without losing legacy decode. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the original descriptor layout and reserve a high metadata flag while leaving transport flags and geometry available for SRAM-direct support. Check a root capability as well as the separate pool block so stale SRAM from a rolled-back image cannot enable extended submissions. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the host integration test aligned with the firmware source-adapter boundary. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Use full-width AV1 and VP9 work counters so 256-tile frames do not wrap to zero before preparing queue metadata. Iterate continuations without unsigned subtraction and add a builder regression for the 256-work case. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Integrate avd/rewrite-integ SRAM transport, mailbox fixes and PM recovery. Preserve strict per-context dependencies, add a bounded asynchronous SRAM producer and negotiate firmware-selected VP pools. Reject invalid ring geometry and reset before retiring rejected or fatal work. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Preserve integration recovery-storm handling and immediate errors for faulted decoders, together with FIFO-bounded admission and conservative context dependencies. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
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Superseded by avd/rewrite-integ-mvp3, which ports multi-VP dispatch onto the merged rewrite (#713). It lands as one follow-up series once it passes on the J616s. |
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The open compatibility transport admits one frame and retains the m2m job until PP completes, preventing separate contexts from using different VPs. This change caps admitted slots at min(16, fifo_slots, backend limit), describes codec VP pool bases/counts in match data and submits tagged programs to firmware-selected engines. Completed pictures release the m2m job once slots own their buffers.
H.264 and HEVC retain AVD_DEP_PREV_DONE. Same-stream VP independence and mutable scratch safety are unproven; separate contexts can overlap. Codecs explicitly provide PP counts, including one PP execution for multi-slice H.264 and full-width 256-tile AV1/VP9 counts. Fatal or rejected firmware records reset the whole decoder before buffer retirement.
This branch merges avd/rewrite-integ at 422060f from #713, preserving SRAM transport, FIFO scratch banking, mailbox fixes, recovery-storm pacing and accepted power recovery. A bounded nonblocking producer streams long programs from queue work, allowing completion IRQs to take the queue mutex. The advertised SRAM ring must have power-of-two geometry to preserve count-to-slot mapping across u32 wrap. Program delivery does not require PIODMA or a second DART stream. Ordinary decoder DMA ownership remains mandatory.
Matching firmware draft: aurora-silicon/avd-fw#5, incorporating the ABI 2 source from aurora-silicon/avd-fw#4. Root capability bit 31 and an AVM1 block negotiate context/dependency, FIFO IOVA and PP count metadata. Stale SRAM cannot enable metadata after image rollback. Unmarked ABI 2 images retain legacy PP fields; incompatible images retain the compatibility transport. T6020 selects v3-t2; T6040 selects v5-t2 and retains its explicit h265 capability requirement.
Validation: production host helpers pass 100,000 shuffled operations and 36,424 ordered retirements. A second host test links those helpers to the real firmware scheduler and passes two contexts on VP0/VP1 across all eight image tables, FIFO limits, metadata rollback rejection, SRAM producer count wrap and ordered tags. Firmware Make/Meson/layout/Unicorn checks pass for eight images and both program sources. KUnit FIFO-admission, PP-count, ring-boundary and metadata cases are added. Checkpatch has no errors and one generic new-file MAINTAINERS reminder. Controller ARM64 W=1 WERROR builds remain queued; KUnit execution and kernel build success are not claimed. A host-only Fedora 6.17 header build was incompatible with this kernel 7.3 branch and is not qualification evidence.
No decoder hardware or throughput measurement was used. avd-multi-vp.rst gives exact avd-bench N=1,2,4 commands through tests/run-multi-stream.sh, retaining per-stream pixel checks, hashes and failures. Lead device validation remains required.