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arm64: dts: apple: Add the T6050 (M5 Ultra) and the Mac Studio (J775D) device tree - #897

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funkzy wants to merge 5 commits into
aurora-silicon:t6050/basefrom
funkzy:pr/t6050-j775d-dt
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funkzy wants to merge 5 commits into
aurora-silicon:t6050/basefrom
funkzy:pr/t6050-j775d-dt

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@funkzy

@funkzy funkzy commented Nov 3, 2026

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This adds a first device tree for the M5 Ultra and its Mac Studio: enough to boot a distribution from the internal
disk, with the console on the USB debug link and networking on the onboard Ethernet.

Depends on #889 (apple,tx-never-wait), #890 (T6050 DARTs and the PCIe hosts the boot loader trained) and #891
(the T6050 SART and ANS). Its DTB validates against those bindings with no warnings.

Commits:

  1. dt-bindings: arm: apple: the J775D board and the T6050 SoC compatibles.
  2. dt-bindings: interrupt-controller: apple,aic2: apple,t6050-aic3. It takes the T8122 fallback and, like T6031's,
    four interrupt cells (the second cell is the die).
  3. dt-bindings: watchdog: apple,wdt: apple,t6050-wdt, compatible with T8103's.
  4. dt-bindings: mailbox: apple,mailbox: apple,t6050-asc-mailbox, an ASC v4 mailbox.
  5. arm64: dts: apple: t6050.dtsi and t6050-j775d.dts.

t6050.dtsi describes the 30 CPUs (spin-table, started by the boot loader), the AIC3 for both dies, the timer, the
DockChannel UART, the watchdog (the restart handler), the storage SART, the ANS mailbox and NVMe controller, the
DARTs of PCIe ports 2 and 3, and one bus per die (the boot loader looks up each die's bus). t6050-j775d.dts adds
the PCIe host with the two root ports the boot loader trains: port 2 with the RTL8127A 10 Gb Ethernet (its MAC
address comes from the boot loader through the ethernet0 alias) and port 3 with the ASM3142 xHCI behind the rear
USB-A ports. It enables the console with apple,tx-never-wait: the debug link drains only while a host reads it, and
the machine also boots unattended with nothing attached there.

Not described yet, each with its own follow-up once its bindings land: the SMC (RTC, SMC power off, sensors; it
needs #479 plus the T6050 reboot and RTC cells, and the PMU's cells on SPMI, #477), the GPU, the display and Type-C
chain (#480, #485), the memory cache controller and the PMC. Until the SMC is described, the watchdog restarts the
machine, power off halts, and there is no RTC.

Testing: on a Mac Studio (M5 Ultra), on t6050/base with #889, #890 and #891: make dtbs_check reports nothing
for t6050-j775d.dtb and no change for any other Apple DTB; dt_binding_check is clean. A warm reboot from another
kernel into this one brought Arch Linux ARM up from the internal NVMe disk with both PCIe ports (the Ethernet linked
at 1 Gbps; the xHCI enumerated) and SSH; console writes with nothing reading the debug link took 3 ms for 20 lines;
a warm reboot out through the watchdog took 37 s with no stop timeouts.

cc @DjDeveloperr: the four SoC enum entries (board, AIC3, watchdog, ASC mailbox) are generic T6050 facts; the APIF
device trees can use them too.

funkzy and others added 5 commits November 2, 2026 16:24
Add the J775D board and its T6050 (M5 Ultra) SoC.

Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
T6050's AIC3 is the T8122 one with two dies, so it takes the T8122 fallback
and, like T6031's, four interrupt cells (the second is the die).

Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
T6050's watchdog is compatible with T8103's.

Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
T6050's coprocessors (ANS among them) use the ASC v4 mailbox.

Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Add a first device tree for the M5 Ultra and its Mac Studio: enough to
boot a distribution from the internal disk with the console on the USB
debug link and networking on the onboard Ethernet.

t6050.dtsi describes the 30 CPUs (spin-table, started by the boot
loader), the AIC3 for both dies, the timer, the DockChannel UART, the
watchdog (the restart handler), the storage SART, the ANS mailbox and
the NVMe controller, the DARTs of PCIe ports 2 and 3, and one empty bus
per die.

t6050-j775d.dts adds the PCIe host with the two root ports the boot
loader trained: port 2 with the RTL8127A 10 Gb Ethernet and port 3 with
the ASM3142 xHCI behind the rear USB-A ports. It enables the console with
apple,tx-never-wait: the debug link drains only while a host reads it,
and the machine boots unattended with nothing attached there.

Not yet described: the SMC (RTC, power off, sensors), the PMU, the GPU,
the display and the Type-C ports. Until the SMC is described, the
watchdog restarts the machine and the RTC is not available.

Signed-off-by: Jeff Queisser <funkzy@users.noreply.github.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@funkzy

funkzy commented Nov 3, 2026

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Closing: this change now lives in the funkzy/j775d branch of aurora-silicon/linux-aurora (the J775D series as built and booted, 681521644671), which dj merges directly; no PR flow for it any more.

@funkzy funkzy closed this Nov 3, 2026
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