Ensure that op_Equality/Inequality can actually import as expected

[tannergooding]

The lack of the flag was blocking correct handling of op_Equality and op_Inequality for certain generic contexts (typically involving ISimdVector) as it would attempt to resolve using the wrong class handle.

This resolves #93174

[Copilot]

Pull request overview

This PR updates the JIT hardware-intrinsic metadata so the Vector* op_Equality / op_Inequality intrinsics derive their SIMD base type from the first argument (instead of falling back to return type / owning type), which is required for correct import/lowering of these boolean-returning SIMD operators.

Changes:

• Add HW_Flag_BaseTypeFromFirstArg to Vector128/256/512.op_Equality and Vector128/256/512.op_Inequality on xarch.
• Add HW_Flag_BaseTypeFromFirstArg to Vector64/128.op_Equality and Vector64/128.op_Inequality on arm64.

Show a summary per file

File	Description
src/coreclr/jit/hwintrinsiclistxarch.h	Marks Vector128/256/512 equality/inequality operators as base-type-from-arg so import/lowering has the correct SIMD base type.
src/coreclr/jit/hwintrinsiclistarm64.h	Marks Vector64/128 equality/inequality operators as base-type-from-arg so import/lowering has the correct SIMD base type.

Copilot's findings

• Files reviewed: 2/2 changed files
• Comments generated: 0

[EgorBo]

Probably closes #93174

[tannergooding]

windows arm64

Overall (-13,900 bytes)
MinOpts (-24 bytes)
FullOpts (-13,876 bytes)

windows x64

Overall (-74,512 bytes)
MinOpts (-176 bytes)
FullOpts (-74,336 bytes)

With throughput improvements up to -0.17%.

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We get some really big diffs like

-1,024 (-73.14%) : 39499.dasm - System.Globalization.Ordinal:EqualsIgnoreCase_VectorSystem.Runtime.Intrinsics.Vector128`1[ushort]:bool (Tier1)

Where the improvement is because the API no longer hits an unrolled loop and just emits the 1-2 instructions as expected

[tannergooding]

/ba-g unrelated timeouts