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[LoongArch64] Fix the GCReg update for the relocation case (pcalau12i + addi.d/ld.d) of NativeAOT, the GCReg should update after calculation completed. #132963

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Merged
jakobbotsch merged 1 commit into from
Aug 31, 2026
+16 −2
Merged

[LoongArch64] Fix the GCReg update for the relocation case (pcalau12i + addi.d/ld.d) of NativeAOT, the GCReg should update after calculation completed. #132963

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7 changes: 5 additions & 2 deletions src/coreclr/jit/codegenloongarch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -974,7 +974,8 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size,
if (EA_IS_RELOC(size))
{
assert(genIsValidIntReg(reg));
emit->emitIns_R_AI(INS_bl, size, reg, imm); // for example: EA_PTR_DSP_RELOC
// for example: EA_PTR_DSP_RELOC
emit->emitIns_R_AI(INS_bl, size, reg, imm DEBUGARG(targetHandle) DEBUGARG(gtFlags));
}
else
{
Expand Down Expand Up @@ -3698,7 +3699,9 @@ void CodeGen::genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize,
if (m_compiler->opts.compReloc)
{
// TODO-LOONGARCH64: here the bl is special flag rather than a real instruction.
GetEmitter()->emitIns_R_AI(INS_bl, EA_PTR_DSP_RELOC, callTargetReg, (ssize_t)pAddr);
GetEmitter()->emitIns_R_AI(INS_bl, EA_PTR_DSP_RELOC, callTargetReg,
(ssize_t)pAddr DEBUGARG((size_t)m_compiler->eeFindHelper(helper))
DEBUGARG(GTF_ICON_METHOD_HDL));
}
else
{
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11 changes: 11 additions & 0 deletions src/coreclr/jit/emitloongarch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2094,6 +2094,11 @@ void emitter::emitIns_R_AI(instruction ins,
id->idOpSize(EA_PTRSIZE);
}

#ifdef DEBUG
id->idDebugOnlyInfo()->idMemCookie = targetHandle;
id->idDebugOnlyInfo()->idFlags = gtFlags;
#endif

id->idAddr()->iiaAddr = (BYTE*)addr;
id->idCodeSize(8);

Expand Down Expand Up @@ -3881,6 +3886,12 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
// for stores, but we ignore those cases here.)
if (emitInsMayWriteToGCReg(ins)) // True if "id->idIns()" writes to a register than can hold GC ref.
{
if (INS_OPTS_RELOC == id->idInsOpt())
{
// For relocation case (pcalau12i + addi.d/ld.d), the GCReg should update after calculation completed.
dstRW2 += 4;
}

// We assume that "idReg1" is the primary destination register for all instructions
if (id->idGCref() != GCT_NONE)
{
Expand Down
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