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Resynthesis

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julianspeith edited this page Aug 12, 2026 · 2 revisions

The resynthesis plugin rewrites parts of a netlist into a different, simpler form while preserving what they compute. It can either decompose gates into elementary Boolean operations, or hand a subcircuit to Yosys to be re-synthesized against a reduced gate library of your choosing.

This plugin is not built by default. Rebuild HAL with -DBUILD_ALL_PLUGINS=ON or -DPL_RESYNTHESIS=ON, see Building HAL. Re-synthesis additionally requires Yosys to be installed and available on your system; decomposition does not.

Why this matters

The gate library a design was synthesized for is a poor basis for analysis. Vendor libraries contain hundreds of cells — AOI221, MUX4, FA1 — chosen for area and timing, not for comprehensibility, and each carries its own pin naming and Boolean function. Two circuits computing the same thing can look entirely different simply because the synthesizer picked different cells.

Normalizing a netlist onto a small, uniform cell set removes that variation. It makes structural comparison meaningful, makes pattern matching feasible, and makes downstream analyses simpler because they only have to understand a handful of gate types. It is also the practical answer to technology-dependent tooling: an analysis that only supports one gate library can be applied to a foreign netlist by re-synthesizing it into that library first.

The flip side is that re-synthesis destroys the original structure. Gate identity, naming, and the exact boundaries of the logic are replaced. Work on a copy — netlist.copy(), see Netlist — if you still need the original.

Decomposition

Decomposition rewrites a combinational gate into a small circuit of AND, OR, XOR, and INVERT gates. It needs no external tools and no target library, which makes it the cheaper of the two mechanisms.

from hal_plugins import resynthesis

resynthesis.decompose_gate(netlist, gate)                       # one gate
resynthesis.decompose_gates_of_type(netlist, [aoi_type, oai_type])   # all gates of these types
  • decompose_gate(nl, gate, delete_gate=True) returns True on success. Set delete_gate=False to keep the original gate in the netlist alongside its decomposition.
  • decompose_gates_of_type(nl, gate_types) returns the number of decomposed gates, or None on failure.

Use this to eliminate complex compound cells before a structural analysis. An AOI221 reduced to plain ANDs, ORs, and inverters is directly comparable to logic that was synthesized differently.

Re-synthesis

Re-synthesis takes a functional description of the selected gates, feeds it to Yosys, and maps the result back onto a target gate library that must be a subset of the library the netlist was parsed with.

resynthesis.resynthesize_gate(netlist, gate, target_gl)
resynthesis.resynthesize_gates(netlist, gates, target_gl)
resynthesis.resynthesize_gates_of_type(netlist, gate_types, target_gl)
resynthesis.resynthesize_subgraph(netlist, subgraph, target_gl)
resynthesis.resynthesize_subgraph_of_type(netlist, gate_types, target_gl)
Function Scope
resynthesize_gate A single gate. Returns True on success; delete_gate=True by default
resynthesize_gates A list of gates, each handled individually
resynthesize_gates_of_type All combinational gates of the given gate types
resynthesize_subgraph A list of gates treated as one connected subgraph, written out as a Verilog netlist and re-synthesized as a whole
resynthesize_subgraph_of_type The subgraph induced by all gates of the given types

All except resynthesize_gate return the number of re-synthesized gates, or None on failure.

The distinction between the gate-wise and subgraph variants matters. Handling gates individually preserves the boundaries between them, so the result maps one-to-one back onto the original. Treating them as a subgraph lets Yosys optimize across those boundaries, which produces a smaller and often much clearer circuit — but the correspondence to the original gates is gone.

The target library

The target library must be a subset of the netlist's own gate library, because the resulting gates have to remain instantiable in the same netlist. In practice you construct a reduced library containing only the cells you want to see in the output — typically a basic set such as inverter, AND, OR, and XOR.

Because Yosys needs the library in genlib format, the genlib writer plugin is what makes this path work.

Practical notes

  • Copy first. Both mechanisms modify the netlist in place and discard the original gates by default.
  • Decompose before you re-synthesize. Decomposition is free and often enough on its own; reach for Yosys only when you actually need mapping onto a specific cell set.
  • Expect gate counts to grow. A compound cell decomposed into elementary gates becomes several gates. This is the intended trade: more gates, simpler gates.
  • Re-synthesis is slow, since it spawns an external process per invocation. Prefer the batch variants over calling the single-gate function in a loop.

See also

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