Add SVE2 optimizations for SynetConvolution16bNhwcGemmV0 - #852
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Port NHWC GEMM bf16 convolution to SVE/SVE2/SVE-BF16 with svbfdot microkernels, wire SynetConvolution16bInit dispatch (keeping Neon SpecV0), extend AutoTests, update VS2022 Sve2 project files, and release 7.2.165 notes. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
ermig1979
marked this pull request as ready for review
August 13, 2026 06:34
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Summary
Adds SVE/SVE2/SVE-BF16 optimizations for
Base::SynetConvolution16bNhwcGemmV0on ARM/ARM64.SimdSve2SynetConvolution16bNhwcGemmV0.cpp— convert/reorder, 2×M microkernels (F=svcntw(),microM=5,microK=2) withsvbfdot, Term16b save helpersSve2::SynetConvolution16bInitselectsSve2::SynetConvolution16bNhwcGemmV0when preferable; keeps Neon SpecV0 for shapes where SpecV0 is preferableSve2::SynetConvolution16bNhwcGemmV0inSimdSynetConvolution16b.hTestSynetConvolution16b.cppSve2.vcxproj/.filtersdocs/2026.htmlTest plan
SIMD_SVE2=ON./Test "-r=.." -fi=SynetConvolution16b -tt=1 -ts=1Sve2::NhwcGemmV0for NHWC group=1 (non-SpecV0) shapes and matches Base within EPS