Add SVE2 optimizations for SynetConvolution16bNhwcSpecV0 - #853
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ermig1979 merged 1 commit intoAug 13, 2026
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Port NHWC SpecV0 bf16 convolution to SVE/SVE2/SVE-BF16 with svbfdot microkernels, wire SynetConvolution16bInit dispatch, extend AutoTests, update VS2022 Sve2 project files, and release 7.2.165 notes. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
ermig1979
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August 13, 2026 07:20
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Summary
Adds SVE/SVE2/SVE-BF16 optimizations for
Base::SynetConvolution16bNhwcSpecV0on ARM/ARM64.SimdSve2SynetConvolution16bNhwcSpecV0.cpp— convert/reorder preprocess, 2×M convolution microkernels (F=svcntw(),microS=5,microC=F*2) withsvbfdot, and Term16b postprocessSve2::SynetConvolution16bInitselectsSve2::SynetConvolution16bNhwcSpecV0when preferable (replacing the previous Neon SpecV0 fallback)Sve2::SynetConvolution16bNhwcSpecV0inSimdSynetConvolution16b.hTestSynetConvolution16b.cppSve2.vcxproj/.filtersdocs/2026.htmlTest plan
SIMD_SVE2=ON(aarch64-linux-gnu-g++,-march=armv9-a+sve+sve2+i8mm+bf16)-cpu max,sve128=on):./Test "-r=.." -fi=SynetConvolution16b -tt=1 -ts=1NEON SVE(128) SVE2 SVE-I8MM SVE-BF16; API path timings match Sve2 column (including SpecV0 3×3 / 5×5 shapes such as112x3x3,128x20x20-96x3x3,192x5x5)