Add SVE2 optimizations for SynetQuantizedMergedConvolution Cdc/Cd/Dc - #856
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Implement SVE/SVE2 kernels for quantized merged convolution input GEMM, depthwise (any/3x3), output GEMM, and residual add, and wire them into Init, tests, VS2022 project files, and release 7.2.165 notes. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
Pass bias/norm as individual svint32_t/svfloat32_t values instead of arrays or pointer arithmetic, which GNU C++ rejects for SVE types. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
ermig1979
marked this pull request as ready for review
August 13, 2026 09:16
QuntizedTerm8i and residual add used Round (half away from zero), which disagrees with Base::NearByInt / NEON NearbyInt on ties and caused off-by-one errors such as 1x32x56x56-192x1x1-5x2-56x1x1. Co-authored-by: igor.ermolaev <igor.ermolaev@altezza.org>
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Add SVE/SVE2 kernels for quantized merged convolution on ARM/ARM64, covering
SynetQuantizedMergedConvolutionCdc,SynetQuantizedMergedConvolutionCd, andSynetQuantizedMergedConvolutionDc.Changes
Set4+Madd4), depthwise preprocess/any/3x3 (Madd2on packed int16 rows), output 1x1 GEMM, and residualAddInputToOutput.SimdSynetQuantizedMergedConvolutionInit(SIMD_SVE2_FUNCbefore NEON).Simd::Sve2::SynetQuantizedMergedConvolutionInitwith the public Init.Sve2.vcxproj/.filtersentries and release 7.2.165 notes indocs/2026.html.NearbyInt(svrintn+ convert, ties to even) to matchBase::NearByIntand NEONNearbyInt. The previousRound(half away from zero) caused off-by-one errors such as1x32x56x56-192x1x1-5x2-56x1x1.Based on
dev(including NEON quantized merged convolution). Vector-length agnostic (svcntw()asmiC).AArch64 cross-compile of the new SVE2 sources and the corresponding test translation unit succeeds with
-march=armv9-a+sve+sve2+i8mm+bf16. This environment is x86_64, so native SVE2Testwas not run. Please re-run./Test "-r=.." -fi=SynetQuantizedMergedConvolutionon ARM.