Update: prewarm each chip with one internal TMR task - #2138
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📝 WalkthroughWalkthroughThe change adds one-time per-chip prewarm dry runs. Runtime flags propagate through native-run preparation, tracing, scheduling, dispatch, validation, and timing analysis. Prewarm dispatches use protocol no-ops and do not count as official rounds. ChangesPrewarm dry-run execution
Estimated code review effort: 4 (Complex) | ~45 minutes Merge Risk: 🔵 Low · up to Prewarm-only traces can produce a misleading diagnostic that says no trace markers were found. This does not affect execution or timing calculations, but should be clarified for benchmark users. Sequence Diagram(s)sequenceDiagram
participant ChipRunLane
participant ChipWorker
participant Runtime
participant SchedulerContext
participant TraceRecorder
ChipRunLane->>ChipWorker: prepare prewarm native run
ChipWorker->>Runtime: pass NativeRunDescriptor.flags
Runtime->>SchedulerContext: propagate prewarm run flags
SchedulerContext->>SchedulerContext: emit zero-address protocol no-op
Runtime->>TraceRecorder: emit chip.prewarm spans
ChipRunLane->>ChipWorker: finalize dry run
ChipRunLane->>ChipWorker: prepare official run
Poem
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 21.10% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 109 functions across 37 files. (1 skipped: 1 unsupported.) Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out. Comment |
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Inline comments:
In `@simpler_setup/tools/strace_timing.py`:
- Line 672: Update the empty run_buckets handling in the trace-reporting logic
to print a distinct message indicating that no official [STRACE] rounds were
found, while preserving the existing “No [STRACE] markers found.” message for
empty buckets input.
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📒 Files selected for processing (38)
docs/testing.mdsimpler_setup/tools/strace_timing.pysrc/a2a3/runtime/host_build_graph/host/runtime_maker.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_context.hsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/host/runtime_maker.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/shared/runtime.cppsrc/a5/runtime/host_build_graph/host/runtime_maker.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_context.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_ready.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_types.hsrc/a5/runtime/tensormap_and_ringbuffer/host/runtime_maker.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/shared/runtime.cppsrc/common/host_build_graph/runtime.hsrc/common/host_build_graph/shared/runtime.cppsrc/common/platform/onboard/host/c_api_shared.cppsrc/common/platform/sim/host/c_api_shared.cppsrc/common/worker/chip_run_lane.cppsrc/common/worker/chip_worker.cppsrc/common/worker/chip_worker.hsrc/common/worker/native_run_trace.hsrc/common/worker/runtime_c_api.htests/ut/cpp/a5/test_hbg_scheduler_ready.cpptests/ut/cpp/common/test_native_run_acceptance.cpptests/ut/cpp/hierarchical/test_chip_run_lane.cpptests/ut/py/test_chip_worker.pytests/ut/py/test_strace_timing.py
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Run one internal zero-address TMR task before the first activated ChipWorker dispatch to cover handshake, scheduler dispatch, and completion without invoking user orchestration or executing a user kernel. Skip unsupported runtimes such as HBG, keep prewarm diagnostics separate from official runs, exclude prewarm invocations from benchmark round statistics, and preserve pipeline accounting.
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Summary
chip.prewarm.run; benchmark round statistics accept only invocations whose depth-0 root is the officialchip.runValidation
mainat5d046b19test_strace_timing.py: 59/59 passedtest_chip_run_laneandtest_native_run_acceptance: 2/2 passedNotes
.claude,scene_test.py, HBG runtime, Qwen example, or PyPTO upper-layer changes are included