Skip to content

freedreno: add unofficial experimental support for Adreno 850 #104

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
lfdevs merged 1 commit into from
Sep 29, 2026
Merged

freedreno: add unofficial experimental support for Adreno 850 #104

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 23 additions & 0 deletions src/freedreno/common/freedreno_devices.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1604,5 +1604,28 @@
raw_magic_regs = a8xx_base_raw_magic_regs,
))

add_gpus([
GPUId(chip_id=0x44051401, name="Adreno (TM) 850"), # DRM/MSM
GPUId(chip_id=0xffff44051401, name="Adreno (TM) 850"), # DRM/MSM fuse fallback
GPUId(chip_id=0xffff44051431, name="Adreno (TM) 850"), # KGSL
], A6xxGPUInfo(
CHIP.A8XX,
[a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2,
GPUProps(shading_rate_matches_vk = True)],
num_ccu = 6,
num_slices = 3,
tile_align_w = 96,
tile_align_h = 32,
tile_max_w = 16416,
tile_max_h = 16384,
num_vsc_pipes = 32,
cs_shared_mem_size = 32 * 1024,
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
highest_bank_bit = 16,
magic_regs = dict(),
raw_magic_regs = a8xx_base_raw_magic_regs,
))

if __name__ == "__main__":
main()
8 changes: 8 additions & 0 deletions src/freedreno/registers/adreno/a6xx.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -269,6 +269,7 @@ by a particular renderpass/blit.
<reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/>
<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/>
<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/>
<reg32 offset="0x084a" name="CP_MULTIDRAW_CNTL" variants="A8XX-"/>
<reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/>

<bitset name="a6xx_cp_protect_cntl" inline="yes">
Expand Down Expand Up @@ -1326,6 +1327,7 @@ by a particular renderpass/blit.

<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
<reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/>
<reg32 offset="0x0df8" name="VSC_VISIBILITY_FLUSH_CNTL" variants="A8XX-"/>
<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="cmd" variants="A6XX-A7XX">
<bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
<bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
Expand Down Expand Up @@ -4384,6 +4386,7 @@ by a particular renderpass/blit.
<reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/>
<reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/>
<reg32 offset="0xae0c" name="SP_STATUS"/>
<reg32 offset="0xae0e" name="SP_L0_PERF_TUNE" variants="A8XX-"/>

<reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init">
<!-- some perfcntrs are affected by a per-stage enable bit
Expand Down Expand Up @@ -4421,6 +4424,7 @@ by a particular renderpass/blit.

<reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/>
<reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/>
<reg32 offset="0xae14" name="SP_CHICKEN_BITS_5" variants="A8XX-"/>
<reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/>
<reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/>
<reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/>
Expand Down Expand Up @@ -5126,6 +5130,10 @@ by a particular renderpass/blit.
<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
<reg32 offset="0x0083" name="CX_MISC_GFX_PWR_CLK_STATUS" variants="A8XX-">
<bitfield name="GX_GDSC_POWER_OFF" pos="3" type="boolean"/>
<bitfield name="GX_CLK_OFF" pos="4" type="boolean"/>
</reg32>
<reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/>
<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
<bitfield pos="0" name="FASTBLEND" type="boolean"/>
Expand Down
1 change: 1 addition & 0 deletions src/freedreno/vulkan/msm_kgsl.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -249,6 +249,7 @@ enum kgsl_user_mem_type {
#define KGSL_UBWC_4_0 4
#define KGSL_UBWC_5_0 5
#define KGSL_UBWC_6_0 6
#define KGSL_UBWC_7_0 7

/*
* Reset status values for context
Expand Down
1 change: 1 addition & 0 deletions src/freedreno/vulkan/tu_knl_kgsl.cc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1961,6 +1961,7 @@ tu_knl_kgsl_load(struct tu_instance *instance, int fd)
case KGSL_UBWC_4_0:
case KGSL_UBWC_5_0:
case KGSL_UBWC_6_0:
case KGSL_UBWC_7_0:
device->ubwc_config.bank_swizzle_levels = 0x6;
device->ubwc_config.macrotile_mode = FDL_MACROTILE_8_CHANNEL;
break;
Expand Down