x86: Enable PAT for write-combining mappings - #147
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jakogut
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September 22, 2026 04:22
Enable MTRR and PAT in the generic and Windows kernel configurations to match SEV and TDX. CONFIG_X86_PAT depends on CONFIG_MTRR. Without PAT, WC mappings fall back to UC-minus. AMD and Intel userspace drivers use write-combined GPU buffers with virtio native contexts. Venus and virgl also expose write-combined buffer mappings to the guest. The UC-minus fallback makes CPU writes to these buffers expensive. Write-back mappings are unaffected. Tested with AMD native contexts on Strix Halo integrated graphics and an RX 9070 XT discrete GPU. Strix Halo showed about a 95% reduction in RADV command recording CPU time. Intel, Venus and virgl remain untested. Signed-off-by: Joseph Kogut <joseph.kogut@gmail.com>
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Makes sense, nice one here, thanks @jakogut ! |
slp
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Sep 22, 2026
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Enable MTRR and PAT in the generic and Windows kernel configurations to match SEV and TDX. CONFIG_X86_PAT depends on CONFIG_MTRR. Without PAT, WC mappings fall back to UC-minus.
AMD and Intel userspace drivers use write-combined GPU buffers with virtio native contexts. Venus and virgl also expose write-combined buffer mappings to the guest. The UC-minus fallback makes CPU writes to these buffers expensive. Write-back mappings are unaffected.
Tested with AMD native contexts on Strix Halo integrated graphics and an RX 9070 XT discrete GPU. Strix Halo showed about a 95% reduction in RADV command recording CPU time. Intel, Venus and virgl remain untested.
Signed-off-by: Joseph Kogut joseph.kogut@gmail.com